Cypress Semiconductor FX2LP Informacje Techniczne Pobierz pdf (Strona 53)

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Chapter 1. Introducing EZ-USB FX2 Page 1-27

Figure 1-17. FX2 FIFOs in “GPIF Master” Mode

External systems that connect to the FX2 FIFOs must provide control circuitry to select FIFOs,

check flags, clock data, etc. FX2 contains a sophisticated control unit (the General Programmable

Interface, or GPIF) which can replace this external logic. In the “GPIF Master” FIFO mode,

(Figure 1-17), the GPIF reads the FIFO flags, controls the FIFO strobes, and presents a user-cus-

tomizable interface to the outside world. The GPIF runs at a very high speed (up to 48 MHz clock

rate) so that it can develop high-resolution control waveforms. It can be clocked from one of two

internal sources (30 or 48 MHz) or from an external clock.

Control (CTL) signals are programmable waveform outputs, and ready (RDY) signals are input

pins that can be tested for conditions that cause the GPIF to pause and resume operation, imple-

FIFO

FD[15:0]

Data

EP8

EP6

EP4

EP2

GPIF

FLAGS

CTL

RDY

GPIFADR

30 MHz

48 MHz

IFCLK

SLRD

8051 RDY

8051 INT

select

SLWR

SLOE

SLRD

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