Cypress Semiconductor FX2LP Informacje Techniczne Pobierz pdf (Strona 413)

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Chapter 15. Registers Page 15-93

4. the rate at which data is being written in exceeds 96 MB/s for a word-wide data bus or

48 MB/s for a byte-wide data bus.

Bits 7-4 HOPERIOD[3:0]

Defines how many IFCLK cycles to assert not ready (HOCTL) to the external master in order

to allow the synchronization interface to catch up.

Bit 3 HOSTATE

Defines what the state of the HOCTL signal should be in to assert not ready.

Bits 2-0 HOCTL[2:0]

Defines which of the six CTL[5:0] pins will be the HOCTL signal which asserts not ready to the

external master when the synchronization detects a potential overflow coming. It should coin-

cide with the CTL[5:0] pin that is picked as the “not ready” signal for the (macro-level) endpoint

FIFO overflow protection.

This register defines whether the Master Strobe (see FLOWSTB) causes data to read or written on

either the falling edge, the rising edge, or both (double-edge).

Bit 1 FALLING

0: data is not transferred on the falling edge of Master Strobe

1: data is transferred on the falling edge of Master Strobe

Bit 0 RISING

0: data is not transferred on the rising edge of Master Strobe

1: data is transferred on the rising edge of Master Strobe

To cause data to transfer on both edges of Master Strobe, set both bits to 1

FLOWSTBEDGE E6CC

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0 0 0 FALLING RISING

R R R R R R R/W RW

0 0 0 0 0 0 0 1

1 2 ... 408 409 410 411 412 413 414 415 416 417 418 ... 459 460

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