Cypress Semiconductor FX2LP Informacje Techniczne Pobierz pdf (Strona 341)

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Chapter 15. Registers Page 15-21

Bit 2 BPPULSE Breakpoint Pulse Mode

Set this bit to “1” to pulse the BREAK bit (and BKPT pin) high for 8 CLKOUT cycles when the

8051 address bus matches the address held in the breakpoint address registers. When this bit

is set to “0”, the BREAK bit (and BKPT pin) remains high until it is cleared by firmware.

Bit 1 BPEN Breakpoint Enable

If this bit is “1”, a BREAK signal is generated whenever the 16-bit address lines match the

value in the Breakpoint Address Registers (BPADDRH:L). The behavior of the BREAK bit and

associated BKPT pin signal is either latched or pulsed, depending on the state of the

BPPULSE bit.

Figure 15-13. Breakpoint Address High

Figure 15-14. Breakpoint Address Low

Bit 15-0 A15:0 High and Low Breakpoint Address

When the current 16-bit address (code or XDATA) matches the BPADDRH/BPADDRL

address, a breakpoint event occurs. The BPPULSE and BPEN bits in the BREAKPT register

control the action taken on a breakpoint event.

BPADDRH Breakpoint Address High E606

b7 b6 b5 b4 b3 b2 b1 b0

A15 A14 A13 A12 A11 A10 A9 A8

R/W R/W R/W R/W R/W R/W R/W R/W

x x x x x x x x

BPADDRL Breakpoint Address Low E607

b7 b6 b5 b4 b3 b2 b1 b0

A7 A6 A5 A4 A3 A2 A1 A0

R/W R/W R/W R/W R/W R/W R/W R/W

x x x x x x x x

1 2 ... 336 337 338 339 340 341 342 343 344 345 346 ... 459 460

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