Cypress Semiconductor FX2LP Informacje Techniczne Pobierz pdf (Strona 395)

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Chapter 15. Registers Page 15-75

Bit 5-4 NPAK1:0 Number of Packets in FIFO

The number of packets in the FIFO. 0-2 Packets.

Bit 3 FULL Endpoint FIFO Full

This bit is set to “1” to indicate that the Endpoint FIFO is full.

Bit 2 EMPTY Endpoint FIFO Empty

This bit is set to “1” to indicate that the Endpoint FIFO is empty.

Bit 0 STALL ENDPOINT STALL

Set this bit to “1” to stall an endpoint, and to “0” to clear a stall.

When the stall bit is “1,” the USB core returns a STALL handshake for all requests to the end-

point. This notifies the host that something unexpected has happened.

15.11.11 Endpoint 6 Control and Status

Figure 15-81. Endpoint 6 Control and Status

Bit 6-4 NPAK2:0 Number of Packets in FIFO

The number of packets in the FIFO. 0-4 Packets.

Bit 3 FULL Endpoint FIFO Full

This bit is set to “1” to indicate that the Endpoint FIFO is full.

Bit 2 EMPTY Endpoint FIFO Empty

This bit is set to “1” to indicate that the Endpoint FIFO is empty.

Bit 0 STALL ENDPOINT STALL

Set this bit to “1” to stall an endpoint, and to “0” to clear a stall.

When the stall bit is “1,” the USB core returns a STALL handshake for all requests to the end-

point. This notifies the host that something unexpected has happened.

EP6CS Endpoint 6 Control and Status E6A5

b7 b6 b5 b4 b3 b2 b1 b0

0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL

R R R R R R R R/W

0 0 0 0 0 1 0 0

1 2 ... 390 391 392 393 394 395 396 397 398 399 400 ... 459 460

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