Cypress Semiconductor FX2LP Informacje Techniczne Pobierz pdf (Strona 173)

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Chapter 9. Slave FIFOs Page 9-17

9.2.10 Implementing Asynchronous Slave FIFO Reads

Figure 9-22. Interface Pins Example: Asynchronous FIFO Reads

Typically, the sequence of events for the external master is:

IDLE: When read event occurs, transition to State 1.

STATE 1: Point to OUT FIFO, assert FIFOADR[1:0], transition to State 2.

STATE 2: If Empty flag is false (FIFO not empty), transition to State 3 else remain in State 2.

STATE 3: Assert SLOE, assert SLRD, sample data on the bus, de-assert SLRD (increment

pointer), de-assert SLOE, transition to State 4.

STATE 4: If more data to read, transition to State 2 else transition to IDLE.

Figure 9-23. State Machine Example: Asynchronous FIFO Reads

FLAGB

FLAGC

SLRD

FIFOADR[1:0]

FD[15:0]

FX2

Slave

Mode

EXT.

Master

FULL

EMPTY

SLOE

State 3

State 2

State 4

Done

Launch

Empty

State 1

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