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2–2 Chapter 2: Designing the System

Design Flow

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

Design Flow

Figure 2–1 depicts the typical flow for embedded system design.

In this flow, you specify the system definition using SOPC Builder. After you define

the SOPC Builder system, SOPC Builder generates the following two kinds of output:

■ The HDL files that the Quartus II software compiles to generate the configuration

file for the FPGA. This Quartus II compilation process is the hardware flow.

■ A system description that the software development tools use to generate a system

library specific to the SOPC Builder system. This system library, also called a board

support package, supports the Nios II processor in running the software. The

Nios II IDE provides an environment in which you can develop software

applications for your system. This Nios II IDE development process is the software

flow.

The output of the hardware flow is an FPGA image that is used to configure the target

device. The output of the software flow is an executable file that the Nios II processor

can run.

Figure 2–1. System Design Flow Using SOPC Builder

Generate System

Make Connections

Select Components

Define System

In SOPC Builder

In Quartus II

software

Compile

Configure FPGA

Debug / Run

Specify Timing Constraints

Edit HDL Files

Create Pin Assignments

In Nios II EDS

Build Software Application

Edit Source Files

Add Source Files

Create FPGA Design Develop Software

System DescriptionHDL Files

FPGA Configuration File

Software Application File

Target Device

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