Cypress Semiconductor Perform CY7C1380D Dokumentacja Pobierz pdf (Strona 31)

Chapter 4: Completing the Quartus II Project 4–3

Complete the Quartus II Project

Preliminary

5. On the File menu, click Save Project to save the top-level schematic with the SOPC

Builder system.

Add Timing Constraints and Compile Your Design

To ensure the design works correctly, you must add explicit timing constraints to the

project. For this tutorial, the timing constraints are available in two files,

neek_hw_lab.sdc and ddr_sdram_phy_ddr_timing.sdc. To add the timing constraint

files to the project, perform the following steps:

1. On the Project menu, click Add/Remove Files in Project. The Settings dialog box

appears.

2. Under Category, expand Timing Analysis Settings and click TimeQuest Timing

Analyzer.

3. In the SDC filename box, select neek_hw_lab.sdc.

4. Click Open.

5. Click Add.

6. Repeat steps 3 to 5 for the file ddr_sdram_phy_ddr_timing.sdc.

Figure 4–2. SOPC Builder System Inserted in Top-Level Project

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Cypress Semiconductor Perform CY7C1380D Dokumentacja Strona 31