Cypress Semiconductor Perform CY7C1380D Dokumentacja Pobierz pdf (Strona 29)

Preliminary

4. Completing the Quartus II Project

In this chapter you complete the Quartus II project by adding the generated SOPC

Builder system to the top-level project and adding timing constraint files to your

project. You compile your project in the Quartus II software to perform analysis,

synthesis, fitting, place-and-route, and timing analysis. Compilation generates an

FPGA image as an SRAM object file (.sof). After you download the FPGA image to

the NEEK, the on-board FPGA functions as a processor custom-made for your

application.

If you wish to work with the .qar provided with the tutorial files, open the .qar in the

Quartus II software and skip directly to “Configure the FPGA” on page 4–4.

Complete the Quartus II Project

This section teaches you how to complete your Quartus II project. It contains the

instructions that show you how to perform the following actions:

1. Open the Quartus II Project Block Diagram

2. Add the SOPC Builder System to the Quartus II Project

3. Add Timing Constraints and Compile Your Design

Open the Quartus II Project Block Diagram

To open the top-level project block diagram, perform the following steps:

1. In the Quartus II software, on the File menu, click Open.

2. Browse to your working directory and double-click neek_hw_lab.bdf. The

neek_hw_lab.bdf Block Design File opens in the Block Editor, as shown in

Figure 4–1.

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 45 46

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Cypress Semiconductor Perform CY7C1380D Dokumentacja Strona 29