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2–4 Chapter 2: Designing the System

Design Strategy

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

Design Strategy

SOPC Builder provides a menu of standard hardware components that you can add to

your system. You can add several instances of each component. The only restriction is

the resources available on your board to implement all of the components you

instantiate in your design.

The NEEK comprises a Cyclone III FPGA Starter Board and an LCD Multimedia High

Speed Mezzanine Card (HSMC) daughtercard in addition to accessories and software.

The following NEEK hardware resources are required to run the design you create in

this tutorial:

■ The following Cyclone III FPGA Starter Board resources are required:

■ Cyclone III EP3C25F324 FPGA

■ Embedded USB-Blaster™ circuitry (including an Altera EPM3128A CPLD)

allowing download of FPGA configuration files through your PC’s USB port

■ 256-Mbit DDR SDRAM

■ 1 MByte of synchronous SRAM

■ 16 MBytes of Intel P30/P33 flash memory

■ 50-MHz on-board oscillator

■ The following LCD daughtercard resources are required:

■ LCD touch-screen 800 × 480 pixel display

■ 10-bit VGA digital access card

The NEEK has additional features, including additional memory, not required to

implement this design.

The SOPC Builder system contains both control path and data path components. The

Nios II processor is the main system controller. It initializes and calibrates the LCD

controller, intercepts user touch input, and initializes the data path. It communicates

with other control path components through Avalon Memory-Mapped (Avalon-MM)

interface ports.The Nios II processor reads the program code from low-latency

SSRAM memory, and the DDR SDRAM holds the video frame buffer. A tristate bridge

component enables pin sharing between the SSRAM memory and the flash memory

on the NEEK.

The Nios II processor sends frame buffer data from the DDR SDRAM to a video

pipeline of specialized Avalon Streaming (Avalon-ST) components that move and

process the pixel data, converting it to video data signals and sending them to the

LCD screen.

The pixels must be rendered on the LCD screen smoothly and without delays. This

design achieves this goal by running the DDR SDRAM at a high clock rate to improve

the performance of the video frame buffer. The DDR SSRAM memory controller

component runs at half rate, and a clock-crossing bridge enables smooth data transfer

between the DDR memory controller and CPU clock domains.

Table 2–1 shows how the individual design requirements for this project are

implemented by specific design strategies, which in turn dictate the components you

add to your system in this tutorial.

1 2 ... 5 6 7 8 9 10 11 12 13 14 15 ... 45 46

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