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Chapter 3: Building the SOPC System 3–9

Coordinate Components in the System

Preliminary

Coordinate Components in the System

This section teaches you how to coordinate the components in your SOPC Builder

system to ensure they work together correctly. It contains the instructions that show

you how to perform the following actions:

1. Specify External Clocks and Clock Connections

2. Reassign Component Base Addresses to Eliminate Memory Conflicts

3. Set Interrupt Priorities

4. Set Arbitration Priorities

5. Specify the Nios II Processor Boot Configuration

Specify External Clocks and Clock Connections

You must create one additional clock in the SOPC Builder system, and connect each

component to the correct clock. One of the output ports of the Quartus II project PLL

connects to the new clock.

The clock source for the full digital picture viewer is the 50-MHz oscillator on the

NEEK board. A PLL in the project that is outside your SOPC Builder system takes the

oscillator clock as input and generates two 100-MHz clocks, a system clock, cpu_clk,

and an external SSRAM clock, ssram_clk. The ssram_clk clocks the SSRAM

memory itself and is not part of the SOPC Builder system. Because the PLL is outside

the SOPC Builder system, clocks that the PLL generates are considered external clocks

to the SOPC Builder system.

The 50-MHz oscillator is also the reference clock frequency for the DDR SDRAM

controller, which runs at 150 MHz. The SDRAM runs its local interface at half-rate

frequency, providing a 75-MHz clock that clocks some of the video pipeline

components, such as the SGDMA component.

Create the new clock, set its frequency, and create clock connections by performing the

following steps:

1. To rename the clk_0 clock to osc_clk, in the Clock Settings box, in the Name

column, double-click clk_0.

2. Type osc_clk to replace the current name clk_0. The name change propagates to

the Clock column entries for the individual components automatically.

3. To add the new cpu_clk clock, in the Clock Settings box, to the right of the clocks

list, click Add. A new clock appears at the bottom of the list, with the name clk_0.

4. To rename the new clk_0 clock to cpu_clk, in the Clock Settings box, in the

Name column, double-click clk_0.

5. Type cpu_clk to replace the current name clk_0.

6. In the MHz column, double-click in the cpu_clk row.

7. Type 100.0 to replace the default frequency of 50.0 MHz.

8. Ensure the value in the Source column is External.

Figure 3–8 shows the SOPC Builder clocks list after you perform these steps:

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 45 46

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Cypress Semiconductor Perform CY7C1380D Dokumentacja Strona 21