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2–6 Chapter 2: Designing the System

Block Diagram

Nios II System Architect Design Tutorial © June 2009 Altera Corporation

Preliminary

Block Diagram

Figure 2–2 shows a high-level block diagram of the system you develop to implement

the design.

As systems get larger and more complicated, it is easier to design at a higher level of

abstraction using—and reusing—IP MegaCore functions and standard components.

SOPC Builder automatically generates the system interconnect fabric, which is the

glue logic required to connect the design blocks together. The system interconnect

fabric manages design issues such as dynamic bus-width matching, interrupt

priorities, and arbitration.

f For additional information about the Altera system interconnect fabric, refer to Avalon

Interface Specifications.

f For additional information about SOPC Builder, refer to the Altera SOPC Builder

literature page.

Figure 2–2. High-Level Block Diagram of Digital Picture Viewer

Video Pipeline Components

To LCD ControllerTo Touch Screen

SGDMA

to FIFO

64-to-32

DFA

LCD

SGDMA

Pixel

FIFO

to DFA

Pixel

Converter

24-to-8

DFA

Video Sync

Generator

CPU/DDR

Clock

Bridge

DDR SDRAM

Controller

CFI Flash

Controller

SSRAM

Controller

Flash/SSRAM

Tristate Bridge

System

Timer

EEPROM

CLK PIO

EEPROM

DATA PIO

System Interconnect Fabric

LCD

DAT PIO

IRQ

PIO

SPI

LCD

CLK PIO

LCD

EN PIO

Nios II/f

Processor

JTAG

UART

To JTAG

To EEPROM ID IC

To SDRAM

Flash Memory

To SSRAM

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 45 46

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