Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Pobierz pdf (Strona 89)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 89 of 92

2.Remove resistor R205.

The RXCLKA+ pin on FPGA(U2) is connected to the input of the second PLL in FPGA(U2). However, the RXCLKA+ output

pin of the CYV15G0404DXB chip is connected to the RXCLKA+ input pin of FPGA(U2). The removal of resistor R205 breaks

this connection and allows FCLKB to be routed through the second PLL.

3. .Configure clocking options to FPGA clock option for Channel A (JP11).

This sets the reference clock for Channel A (REFCLKA) to the FPGA clock (FCLKA). Refer to theCYV15G0404DXB User’s

Guide for further information on clocking options.

4. Configure clocking options to programmable clock option for Channels B, C, D.

The block diagram for the resulting clock circuit is shown in Figure F-4.

Test Procedure

Transmission of the SD-SDI signal may be generated on either channel C or channel D. This application note will describe the

connections and settings required for upconverting an SD-SDI signal transmitted on channel C.

Board Connections

1. Apply power to the board and connect the USB cable between the board and the computer.

2. Connect output OUTC1 to input INB1 using a BNC cable.

3. Connect output OUTA1 to the WFM700 using a BNC cable.

Figure F-5 shows the required board connections.

Figure F-4. Upconversion Clock Circuit

FPGA(U2)

PLL 1 PLL 2 JP11

RXCLKB+

FCLKB+

FCLKA+

FCLKA-

REFCLKA+

REFCLKA-

27MHz

74.17 MHz

RXCLKB * (25/13) FCLKB * (10/7)

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Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Strona 89