Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Strona 37
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Oceniono. / 5. Na podstawie oceny klientów
Quad Independent Channel
HOTLink II™ CYV15G0404DXB
Video PHY Demonstration Board
Page 37 of 92
Figure A-7. Clocking and PSoC
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
LS7652
Cypress Molso n - Flexible Clock & Configu ration
2
07 12
G. Cosens
Si ze Dr aw in g Nu mbe r R evisio n
Date:
File:
Sheet of
Drawn By:Fle xibl e Cl ock & Configur ation .SchDo c
7/ 6/ 2004
B
Linear Systems Ltd.
CLI A
CLIB
CLI C
CLID
MCL ADJ A
MCL ADJ B
MCL ADJC
MCL ADJD
REF CL KA+
REFCLKB+
REF CLKC+
REFCLKD+
I2 SCL
I2 SDA
REFCLK+
3
REFCLK-
4
PROGCS
6
PROGDI
7
PROGSK
8
LOCKED
14
CL OCKOUT-
21
CLOCKO UT+
22
GN DA
32
GN DA
25
FNVCF-
30
FNVCF+
31
WRVCF-
26
WRVCF+
27
VCCA
24
VCCA
1
VCCO
18
VCC
17
VCC
9
GND
10
GN D
33
U10
SY8772 9L
REFCLK+
3
REFCLK-
4
PROGCS
6
PROGDI
7
PROGSK
8
LOCKED
14
CLOCKO UT-
21
CL OCKOUT+
22
GN DA
32
GN DA
25
FNVCF-
30
FNVCF+
31
WRVCF-
26
WRVCF+
27
VCCA
24
VCCA
1
VCCO
18
VCC
17
VCC
9
GND
10
GND
33
U11
SY8772 9L
REFCLK+
3
REFCLK-
4
PROGCS
6
PROGDI
7
PROGSK
8
LOCKED
14
CLOCKO UT-
21
CL OCKOUT+
22
GNDA
32
GNDA
25
FNVCF-
30
FNVCF+
31
WRVCF-
26
WRVCF+
27
VCCA
24
VCCA
1
VCCO
18
VCC
17
VCC
9
GND
10
GN D
33
U13
SY8772 9L
REFCLK+
3
REFCLK-
4
PROGCS
6
PROGDI
7
PROGSK
8
LOCKED
14
CLOCKO UT-
21
CL OCKOUT+
22
GN DA
32
GN DA
25
FNVCF-
30
FNVCF+
31
WRVCF-
26
WRVCF+
27
VCCA
24
VCCA
1
VCCO
18
VCC
17
VCC
9
GND
10
GND
33
U12
SY8772 9L
AI/ P0[7]
1
AIO/P0[5]
2
AIO/P0[3]
3
AI/ P0[1]
4
P2[7]
5
P2[5]
6
AI(ASC1 0)/P2[3]
7
AI(ASD20/ASC10)/P2[1]
8
P4[7]
9
P4[5]
10
P4[3]
11
P4[1]
12
SM P
13
P3[7]
14
P3[5]
15
P3[3]
16
P3[1]
17
P5[3]
18
P5[1]
19
SCL/P1[7]
20
SDA /P1[5]
21
P1[3]
22
SCL/XTALIN/P 1[1]
23
VSS
24
CY8C27643-PVI
P1[0]/XTALOUT/SDA
25
P1[2]
26
P1[4] /EXTC LK
27
P1[6]
28
P5[0]
29
P5[2]
30
P3[0]
31
P3[2]
32
P3[4]
33
P3[6]
34
XRES
35
P4[0]
36
P4[2]
37
P4[4]
38
P4[6]
39
P2[0]/AI(ASC23)
40
P2[2]/AI (ASD13/ ASC23)
41
P2[4] /AI(AGND)
42
P2[6]/AI(Ref)
43
P0[0]/AI
44
P0[2]/AIO
45
P0[4]/AIO
46
P0[6]/AI
47
VDD
48
U14
CY8C2 7643 -24PVI
R25
2.0 K
C48
0.1 u
R26
2.0 K
C49
0.1 u
R29
2.0 K
C58
0.1 u
R30
2.0 K
C59
0.1 u
R23
2.0 K
C43
0.1 u
R24
2.0 K
C44
0.1 u
R27
2.0 K
C53
0.1 u
R28
2.0 K
C54
0.1 u
+3.3V+3.3V
+3.3 V +3.3V
+3.3V +3.3V
+3.3 V+3.3V
SCL
SDO
SCSA
SCSB
SCSD
SCSC
+3.3 V
R41
14 7
R42
147
R51
12 1
R52
121
R33
100
R55
12 1
R56
121
R37
100
R53
121
R54
12 1
R36
100
R49
12 1
R50
121
R32
100
C50
0.1 u
C51
0.1 u
C52
0.1 u
C45
0.1 u
C46
0.1 u
C47
0.1 u
C60
0.1 u
C61
0.1 u
C62
0.1 u
C55
0.1 u
C56
0.1 u
C57
0.1 u
+3.3V
+3.3V
+3.3V
+3.3V
+3.3 V
SCLSDO
SCSA
SCSB SCSC
SCSD
SDI
SDO
SCL
SCSE
SDI
SCSE
OUT
8
VC C
14
GN D
7
OUT
1
X1
27 MHz
R47
14 7
R48
147
R39
14 7
R40
147
+3.3V
R45
14 7
R46
147
R19
0
R21
0
R22
0
R20
0
REFCLKB-
REF CL KA-
REF CLKC-
REFCLKD-
VCCO
1
NC
2
VCC
3
CLK_SEL
4
CLKA
5
CLKA#
6
CLKB
7
CLKB#
8
VEE
9
VCCO
10
VCCO
11
Q3#
12
Q3
13
Q2#
14
Q2
15
Q1#
16
Q1
17
Q0#
18
Q0
19
VCCO
20
U9
CY2DP314OI
R43
82
R44
82
R34
100
R31
100
R35
10 0
R38
100
WRENADDR[3. .0 ]
DATA[7 ..0]
DATA[7 ..0]
DATA0
DATA1 DATA2
DATA3 DATA4
DATA5 DATA6
DATA7
ADDR [3..0]
ADDR0
ADDR1 ADDR2
ADDR3
HRESET# SCSE1
SCSE1
C141
0.1 u
C140
0.1 u
C142
10n
+3.3V
+3.3V
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
LOCKEDA
LOCKEDB
LOCKEDC
LOCKEDD
LOCKEDD
LOCKEDCLOCKEDB
LOCKEDA
1
2
3
4
5
JB5
5PINFL
XRES XRES
XSCLK
XDATA
R198
130
R199
130
+3.3V
XRES
XSCLK
XDATA
R200
1K
FCLK A+
FCLKA-
FCLK B+
FCLK B-
FCLK D+
FCLKD-
FCLK C+
FCLK C-
Place close to H OTLink II
Place close to H OTLink II
Place close to H OTLinkII
Place close to H OTLink II
i
50 ohm
i
50 ohm
JP11
JP12
JP13
JP10
NC
1
NC
2
GN D
3
OUT
4
OUT
5
VC C
6
X5
74 .25 MHz
NC
1
NC
2
GN D
3
OUT
4
OUT
5
VC C
6
X2
74 .25 MHz
NC
1
NC
2
GND
3
OUT
4
OUT
5
VC C
6
X4
74 .25 MHz
NC
1
NC
2
GND
3
OUT
4
OUT
5
VC C
6
X3
74 .25 MHz
+3.3 V
+3.3 V
+3.3 V
+3.3 V
OSCA+
OSCA-
OSCD+
OSCD-
OSCC+
OSCC-
OSCB-
OSCB+
OSCA+
OSCA-
OSCD-
OSCD+
OSCB+
OSCB-
OSCC+
OSCC-
C229
0.1 u
C230
0.1 u
C231
0.1 u
C232
0.1 u
C233
0.1 u
C234
0.1 u
C235
0.1 u
C236
0.1 u
C237
0.1 u
C238
0.1 u
C239
0.1 u
C240
0.1 u
+
C241
10 u
+
C242
10 u
+
C243
10u
+
C244
10 u
+
C245
10u
C246
0.1 u
C247
0.1 u
C248
0.1 u
C249
0.1 u
+3.3 V
R222
0
R223
0
R226
0
R227
0
R230
0
R231
0
R234
0
R235
0
R232
130
R233
130
R220
130
R221
130
R224
130
R225
130
R228
130
R229
130
C278
0.1 u
C279
0.1 u
C280
0.1 u
C281
0.1 u
C282
0.1 u
C283
0.1 u
C284
0.1 u
C285
0.1 u
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
i
50 ohm
[+] Feedback
- Quad Independent Channel 1
- HOTLink II™ CYV15G0404DXB 1
- Video PHY Demonstration Board 1
- Users Guide 1
- Page 2 of 92 2
- Page 3 of 92 3
- LIST OF TABLES 4
- 1.0 Introduction 5
- 2.0 Kit Contents 5
- 3.0 Demo Board Features 6
- 4.0 Board Architecture 7
- 4.2 Clocking Architecture 8
- Programmable 10
- 4.4 Power Supply 11
- 5.0 GUI and Operating Modes 12
- [+] Feedback 13
- 5.1 Setting the SDI Data Rate 14
- 5.3 Standard 15
- 5.4 Transmit Test Pattern 16
- 5.5 Status 16
- 6.0 Sample Test Procedures 17
- 6.3 Tests 19
- Page 23 of 92 23
- Page 24 of 92 24
- Page 27 of 92 27
- Page 28 of 92 28
- 7.0 Summary 29
- 8.0 References 29
- Linear Syst ems Ltd 33
- Page 36 of 92 36
- Page 38 of 92 38
- (GERBER Files) 43
- Page 45 of 92 45
- Figure B-2. Top Overlay 45
- Page 64 of 92 64
- (Drill and Assembly) 65
- Page 66 of 92 66
- Figure C-1. Drill Placement 66
- Page 67 of 92 67
- Figure C-2. Assembly–Top View 67
- Page 68 of 92 68
- Video Demo Board 69
- Setting Configurations 85
- SD-SDI to HD-SDI Upconversion 86
- Channel B 87
- Channel A 87
- FPGA (U2) 87
- Board Modification 88
- FPGA(U2) 89
- PLL 1 PLL 2 JP11 89
- Page 91 of 92 91
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