Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Strona 38
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Quad Independent Channel
HOTLink II™ CYV15G0404DXB
Video PHY Demonstration Board
Page 38 of 92
Figure A-8. HOTLink II CYV15G0404DXB
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
LS7652
Cypr ess Molson - CYV15G0403
2
08 12
G. Cosen s
Size Drawing Number Revisio n
Dat e:
File:
Sheet of
Drawn By:CYV1 5G0403.SchDoc
7/ 6/20 04
B
Linear Syst ems Ltd.
OUTA1+
OUTA1-
OUTA2+
OUTA2-
INA1+
INA1-
INA2+
INA2-
OUTB1+
OUTB1-
OUTB2-
OUTB2+
INB1-
INB2-
INB2+
INB1+
OUTC1+
OUTC1-
OUTC2+
OUTC2-
INC1+
INC1-
INC2+
INC2-
OUTD1+
OUTD1-
OUTD2+
OUTD2-
IND1+
IND1-
IND2+
IND2-
TX DA[7.. 0]
TX DB[7..0 ]
TX DC[7..0 ]
TX DD[7.. 0]
TX CTA[1..0 ]
TX CTB[1..0 ]
TX CTC[1..0 ]
TX CTD[1.. 0]
RXDA[7. .0]
RXDB[7.. 0]
RXDC[7.. 0]
RXDD[7 ..0 ]
RXSTA[2..0]
RXSTB[2..0]
RXSTC[2..0]
RXSTD[2..0]
TX CLKOA
TXCLKOB
TXCLKOC
TXCLKOD
RXCLKA+
RXCLKA-
RXCLKB+
RXCLKB-
RXCLKC+
RXCLKC-
RXCLKD+
RXCLKD-
TXCLKA
TXCLKB
TXCLKC
TXCLKD
REFCLKA+
REFCLKB+
REFCLKC+
REFCLKD+
HRESET#
SPDSELA
SPDSELB
SPDSELC
SPDSELD
LPENA
LPENC
LPENB
LPEND
INSELA
INSELB
INSELC
INSELD
ULCA
ULCB
ULCC
ULCD
DATA[7..0 ]
ADDR[3. .0]
WREN
REFCLKA+
W18
REFCLKA-
Y18
SPDSEL A
G19
TX CLKOA
V12
TX ERRA
W12
TX CLKA
Y11
TXDA0
Y14
TXDA1
U12
TXDA2
W14
TXDA3
V14
TXDA4
U14
TXDA5
Y15
TXDA6
W15
TXDA7
V15
TX CTA0
U15
TX CTA1
U9
OUTA1+
B12
OUTA1-
A12
OUTA2+
B15
OUTA2-
A15
U1 A
CYV1 5G0 403DXB
REFCLKB+
M17
REFCLKB-
M18
SPDSEL B
G17
TX CLKOB
F19
TX ERRB
M19
TX CLKB
M20
TX DB0
R18
TX DB1
R17
TX DB2
P20
TX DB3
P19
TX DB4
P18
TX DB5
P17
TX DB6
L20
TX DB7
R20
TX CTB0
U18
TX CTB1
R19
OUTB1+
B18
OUTB1-
A18
OUTB2+
B20
OUTB2-
A20
U1 B
CYV1 5G0 403DXB
REFCLKC+
L2
REFCLKC-
K2
SPDSEL C
D7
TX CLKOC
R2
TX ERRC
M4
TX CLKC
K4
TX DC0
F3
TX DC1
G4
TX DC2
J3
TX DC3
J4
TX DC4
G3
TX DC5
J2
TX DC6
L4
TX DC7
G1
TX CTC0
K3
TX CTC1
J1
OUTC1+
B2
OUTC1-
A2
OUTC2+
B4
OUTC2-
A4
U1 C
CYV1 5G0 403DXB
REFCLKD+
V1 1
REFCLKD-
U1 1
SPDSELD
C15
TXCLKOD
Y9
TXERRD
Y1 7
TXCLKD
Y2
TXDD0
U1
TXDD1
U2
TXDD2
U3
TXDD3
V1
TXDD4
V2
TXDD5
W1
TXDD6
Y1
TXDD7
W2
TXCTD0
V3
TXCTD1
U4
OUTD1+
B7
OUTD1-
A7
OUTD2+
B10
OUTD2-
A10
U1 D
CYV1 5G0 403 DXB
LPENA
D17
INSELA
D4
INA1+
B11
INA1-
A11
INA2+
B14
INA2-
A14
ULCA
D6
RXDA0
V1 9
RXDA1
W20
RXDA2
U1 7
RXDA3
V1 8
RXDA4
W19
RXDA5
Y2 0
RXDA6
Y1 9
RXDA7
V1 7
LFIA
W17
RXSTA0
V2 0
RXSTA1
U2 0
RXSTA2
U1 9
RXCLKA+
W11
RXCLKA-
Y1 2
RCLKENA
F17
U1 E
CYV1 5G0 403DXB
LPENB
D14
INSELB
C4
INB1+
B17
INB1-
A17
INB2+
B19
INB2-
A19
ULCB
D15
RXDB0
J1 8
RXDB1
G2 0
RXDB2
J2 0
RXDB3
K1 7
RXDB4
K1 8
RXDB5
J1 9
RXDB6
L17
RXDB7
K1 9
LFIB
K2 0
RXSTB0
F20
RXSTB1
F18
RXSTB2
J1 7
RXCLKB+
L18
RXCLKB-
L19
RCLKENB
C14
U1 F
CYV1 5G0 403DXB
LPENC
G18
INSELC
C3
INC1+
B1
INC1-
A1
INC2+
B3
INC2-
A3
ULCC
C7
RXDC0
P2
RXDC1
P1
RXDC2
K1
RXDC3
L1
RXDC4
M1
RXDC5
M2
RXDC6
F1
RXDC7
F2
LFIC
L3
RXSTC0
P3
RXSTC1
P4
RXSTC2
R1
RXCLKC+
R3
RXCLKC-
R4
RCLKENC
M3
U1 G
CYV1 5G0 403DXB
LPEND
C19
INSELD
D3
IND1+
B6
IND1-
A6
IND2+
B9
IND2-
A9
ULCD
C6
RXDD0
Y7
RXDD1
U7
RXDD2
U6
RXDD3
V6
RXDD4
W6
RXDD5
Y6
RXDD6
V4
RXDD7
Y3
LFID
W3
RXSTD0
V7
RXSTD1
W7
RXSTD2
V9
RXCLKD+
Y4
RXCLKD-
W4
RCLKEND
F4
U1 H
CYV1 5G0 403DXB
WREN
G2
AD DR0
U1 0
AD DR1
W10
AD DR2
V1 0
AD DR3
W9
DA TA 0
D1 2
DA TA 1
C12
DA TA 2
D1 1
DA TA 3
C11
DA TA 4
D1 0
DA TA 5
C10
DA TA 6
D9
DA TA 7
C9
RESET
D2
TRST
C18
TMS
C2
TCLK
D1
TDI
C1
TDO
C20
LDTDEN
C17
VCC
A5
VCC
B5
VCC
C5
VCC
D5
VCC
A16
VCC
B16
VCC
C16
VCC
D16
VCC
E1
VCC
E2
VCC
E3
VCC
E4
VCC
E17
VCC
E18
VCC
E19
VCC
E20
VCC
T1
VCC
T2
VCC
T3
VCC
T4
VCC
T17
VCC
T18
VCC
T19
VCC
T20
VCC
Y5
VCC
W5
VCC
V5
VCC
U5
VCC
Y16
VCC
W16
VCC
V16
VCC
U16
GND
A8
GND
B8
GND
C8
GND
D8
GND
A13
GND
B13
GND
C13
GND
D13
GND
H1
GND
H2
GND
H3
GND
H4
GND
H17
GND
H18
GND
H19
GND
H20
GND
N1
GND
N2
GND
N3
GND
N4
GND
N17
GND
N18
GND
N19
GND
N20
GND
Y8
GND
W8
GND
V8
GND
U8
GND
Y13
GND
W13
GND
V13
GND
U13
LTEN1
D1 8
SCANEN2
D1 9
TMEN3
D2 0
U1 I
CYV1 5G0 403 DXB
TXDA0
TXDA1
TXDA2
TXDA3
TXDA4
TXDA5
TXDA6
TXDA[7.. 0] TXDA7
TXCTA0
TXCTA1TXCTA[ 1..0 ]
TXDB0
TXDB1
TXDB2
TXDB3
TXDB4
TXDB5
TXDB6
TXDB7
TXCTB 0
TXCTB 1
TXDB[ 7..0]
TXCTB [1 ..0 ]
TXCTC 0
TXCTC 1
TXDC0
TXDC1
TXDC2
TXDC3
TXDC4
TXDC5
TXDC6
TXDC7
TXDC[ 7..0]
TXCTC [1 ..0 ]
TXDD[7.. 0]
TXCTD[1.. 0]
TXCTD0
TXCTD1
TXDD0
TXDD1
TXDD2
TXDD3
TXDD4
TXDD5
TXDD6
TXDD7
LFIA
LFIB
LFIC
LFID
RXDA0
RXDA1
RXDA2
RXDA3
RXDA4
RXDA5
RXDA6
RXDA7
RXDB0
RXDB1
RXDB2
RXDB3
RXDB4
RXDB5
RXDB6
RXDB7
RXDC0
RXDC1
RXDC2
RXDC3
RXDC4
RXDC5
RXDC6
RXDC7
RXDD0
RXDD1
RXDD2
RXDD3
RXDD4
RXDD5
RXDD6
RXDD7
RXSTA0
RXSTA1
RXSTA2
RXSTB0
RXSTB1
RXSTB2
RXSTC0
RXSTC1
RXSTC2
RXSTD0
RXSTD1
RXSTD2
RXSTD[2 ..0]
RXSTC[2.. 0]
RXSTB[2.. 0]
RXSTA[2..0]
RXDA[7. .0]
RXDB[7.. 0]
RXDC[7.. 0]
RXDD[7 ..0 ]
ADDR[3. .0]
DATA[7..0 ]
+3.3V
ADDR0
ADDR1
ADDR2
ADDR3
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
LDTDEN
LDTDEN
RCLKENA
RCLKENC
RCLKEND
C1
0. 1u
C2
0. 1u
C3
0. 1u
C4
0. 1u
C5
0. 1u
C6
0. 1u
C7
0. 1u
C8
0. 1u
1 2
JP1
HEADER 1X2
1 2
JP2
HEADER 1X2
1 2
JP3
HEADER 1X2
1 2
JP4
HEADER 1 X2
RCLKENB
i
50 ohm
i
50 oh m
i
50 oh m
i
50 ohm
REF C LKA-
REFCLKB-
REFCLKC-
REF C LKD-
TCLK
TDI
TMRESET #
TDO
C159
0. 1u
C160
0. 1u
C161
0. 1u
C162
0. 1u
C163
0. 1u
C164
0. 1u
C165
0. 1u
C166
0. 1u
+3.3V
+
C167
68u
TMS
TXERR A
TXERR B
TXERR C
TXERR D
1 2
JP2 6
HEADER 1 X2
R206
22
R205
22
R207
22
R208
22
R209
22
R210
22
R211
22
R212
22
R201
10
R202
10
R203
10
R204
10
C211
0. 1u
C212
0. 1u
C213
0. 1u
C214
0. 1u
C215
0. 1u
C216
0. 1u
C217
0. 1u
C218
0. 1u
+3.3V +3.3V
C219
0. 1u
C220
0. 1u
C221
0. 1u
C222
0. 1u
C223
0. 1u
C224
0. 1u
C225
0. 1u
C226
0. 1u
C227
1u
C228
1u
[+] Feedback
- Quad Independent Channel 1
- HOTLink II™ CYV15G0404DXB 1
- Video PHY Demonstration Board 1
- Users Guide 1
- Page 2 of 92 2
- Page 3 of 92 3
- LIST OF TABLES 4
- 1.0 Introduction 5
- 2.0 Kit Contents 5
- 3.0 Demo Board Features 6
- 4.0 Board Architecture 7
- 4.2 Clocking Architecture 8
- Programmable 10
- 4.4 Power Supply 11
- 5.0 GUI and Operating Modes 12
- [+] Feedback 13
- 5.1 Setting the SDI Data Rate 14
- 5.3 Standard 15
- 5.4 Transmit Test Pattern 16
- 5.5 Status 16
- 6.0 Sample Test Procedures 17
- 6.3 Tests 19
- Page 23 of 92 23
- Page 24 of 92 24
- Page 27 of 92 27
- Page 28 of 92 28
- 7.0 Summary 29
- 8.0 References 29
- Linear Syst ems Ltd 33
- Page 36 of 92 36
- Page 38 of 92 38
- (GERBER Files) 43
- Page 45 of 92 45
- Figure B-2. Top Overlay 45
- Page 64 of 92 64
- (Drill and Assembly) 65
- Page 66 of 92 66
- Figure C-1. Drill Placement 66
- Page 67 of 92 67
- Figure C-2. Assembly–Top View 67
- Page 68 of 92 68
- Video Demo Board 69
- Setting Configurations 85
- SD-SDI to HD-SDI Upconversion 86
- Channel B 87
- Channel A 87
- FPGA (U2) 87
- Board Modification 88
- FPGA(U2) 89
- PLL 1 PLL 2 JP11 89
- Page 91 of 92 91
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