Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Pobierz pdf (Strona 87)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 87 of 92

Overview

This appendix discusses the necessary modifications that need to be made to the CYV15G0404DXB video demo board, in order

for it to be able to perform upconversion. The upconversion function described in this appendix is for functional verification only.

Due to design constraints, the measured jitter will be higher than normal. If you have any questions about this feature please

contact Cypress’s Application Engineers.

Upconversion

Upconversion is the process of manipulating SD video data to produce an HD version of the same video. An SD signal is scaled

to the desired number of horizontal lines per frame, as well as the appropriate number of pixels per line. The resulting HD signal

can be used to drive a high-resolution projector or monitor.

Upconversion may be used in broadcast situations where SD video masters are provided to stations that wish to broadcast in

HD. For example, if a show is produced in 480 line interlaced and is provided to a station that wishes to broadcast in 1080 line

interlaced, an upconversion would be required. Upconversion can also be used when programming is broadcast in HD, but

advertisements are in SD format. An upconversion will enable the transmission of the advertisements in HD format.

In the CYV15G0404DXB video evaluation board, incoming SDI data that needs to be upconverted is input to the channel B

receiver of the HOTLink II device. The deserialized video data is processed by the FPGA where it is upconverted and transmitted

through the channel A transmitter of the HOTLink II device. The upconversion process is comprised of two primary components:

scaling of the video from 720 by 483 to 1440 by 1035 and conversion of the clock frequency from 27 MHz to 74.25/1.001 MHz.

Figure F-1 shows the block diagram for upconversion through the CYV15G0404DXB video demo board.

Video Scaling

To perform the video scaling, the incoming SDI data is stored and scaled in up to seven line buffers. For each seven lines of SDI

data input, the first six lines are repeated twice, and the seventh line is repeated three times. The result is 15 lines of HD-SDI

data for each seven lines of SDI data in. The original SD-SDI image of 720 by 483 is converted to an HD-SDI image 1440 (720*2)

by 1035 (483*15/7). This changes the aspect ratio of 4:3 (1.333:1) to [4*15]:[3*14] (1.429:1). The resulting image is stretched

vertically by about 7%, but matches the average line and frame rates for incoming and outgoing data. In order to generate HD-

SDI line data, each pixel sample pair is repeated twice as follows.

Yn+1 -> C

n+1

Bn+1

n+1

Figure F-1. SD-SDI to HD-SDI Upconversion Block Diagram

SD-SDI: SMPTE 259

(270 Mb/s)

HD-SDI: SMPTE 292

(1485/1.001 Mb/s)

REFCLK (FPGA Clock)

REFCLK (Programmable Clock)

Channel B

Channel A

FPGA (U2)

27 MHz

74.17 MHz

RXCLKB

[+] Feedback

1 2 ... 82 83 84 85 86 87 88 89 90 91 92

Komentarze do niniejszej Instrukcji

Brak uwag

Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Strona 87

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Zegary ścienne Cypress Semiconductor Quad HOTLink II CYV15G0404RB