Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Pobierz pdf (Strona 88)

Quad Independent Channel

HOTLink II™ CYV15G0404DXB

Video PHY Demonstration Board

Page 88 of 92

Clock Rate Conversion

As part of the upconversion process, the incoming SDI clock rate (27 MHz) must be converted to HD-SDI (half rate at 74.25/1.001

MHz). To achieve this, both PLLs in FPGA(U2) are connected in series to get the correct frequency for transmitting. The 27-MHz

clock rate from RXCLKB+ is passed through FPGA(U2), where the first PLL multiplies RXCLKB+ by 25/13, while the second PLL

multiplies the result by 10/7. This produces the desired half rate frequency of 74.17 MHz (74.25/1.001 MHz), which is sent to the

reference clock for channel A (REFCLKA).

Board Modification

The following describes the board modifications required to achieve the clock rate conversion.

1. Connect JP13 (FCLKB+) and JP1 (RXCLKA+) as indicated in Figure F-2. Refer to Figure F-3 for location of the ground pins.

RXCLKB+ is connected to the first PLL in FPGA(U2), while the output of the PLL is internally connected to FCLKB+. By

connecting JP13 and JP1 as indicated, the output of the first PLL (FCLKB+ output pin) is sent to the input of the second PLL

(RXCLKA+ input pin) in FPGA(U2).

Figure F-2. Upconversion Board Modifications

Figure F-3. Ground Pin Location

Connect JP13

and JP1

Remove

R205

Configure to

FPGA clock

Configure to

programmable

clock

Configure to programmable

clock

Ground Pins

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Cypress Semiconductor Quad HOTLink II CYV15G0404RB Podręcznik Użytkownika Strona 88