Cypress Semiconductor CYV15G0404DXB Podręcznik Użytkownika Pobierz pdf (Strona 9)

CYV15G0404DXB Evaluation Board

Users Guide

Page 9 of 56

Figure 4-4 shows the device configuration and control block diagram. The inputs are the external signals WREN, ADDR[3:0], and

DATA[7:0] and will be described in subsequent sections. The outputs are the internal signals that are described in Table 5-4.

WREN

ADDR[3:0]

DATA[7:0]

Device Configuration and Control Block Diagram

= Internal Signal

RXRATE[A..D]

FRAMCHAR[A..D]

RFEN[A..D]

RXCKSEL[A..D]

RFMODE[A..D][1:0]

RXBIST[A..D]

DECMODE[A..D]

DECBYP[A..D]

SDASEL[A..D][1:0]

RXPLLPD[A..D]

TXRATE[A..D]

TXCKSEL[A..D]

TXBIST[A..D]

OE[A..D][2..1]

PABRST[A..D]

ENCBYP[A..D]

GLEN[11..0]

FGLEN[2..0]

Device Configura-

tion and Control

Interface

Figure 4-4. Device Configuration Control Block Diagram

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Cypress Semiconductor CYV15G0404DXB Podręcznik Użytkownika Strona 9