Cypress Semiconductor CYV15G0404DXB Podręcznik Użytkownika Pobierz pdf (Strona 24)

CYV15G0404DXB Evaluation Board

Users Guide

Page 24 of 56

Cables needed:

• Two SMA-to-SMA coaxial cables

• Power supply cables

• DG2020 cables with appropriate connectors

• Logic analyzer cables with appropriate connectors

7.2.2 Parallel Data Test Set-up

For this test, channels A, B, and C will accept parallel data from the DG2020, transmit and receive the data serially in internal

loopback mode, and output the same parallel data to the Logic Analyzer. Channel D will accept parallel data from the DG2020

and will output the data serially to the Signal Analyzer.

• Channel A—100 MHz in encoder enable mode.

• Channel B—50 MHz in encoder enable mode.

• Channel C—100 MHz in encoder bypass mode.

• Channel D—100 MHz in encoder bypass mode.

This test is separated into two sections (encoder enable mode and encoder bypass mode) because the DG2020 does not have

enough wires to supply data for four channels. Follow the procedure below for the test set-up.

7.2.2.1 Encoder Enable Mode

1. Load the Cypress supplied file 0404EN.PDA in DG2020 data generator. If you are using a different data generator, use a

waveform similar to the one shown in Figure 7-8.

Note. The outputs of the DG2020 for this PDA file are mapped to POD-A bits 0–11. If outputs need to be remapped for a particular

test set-up, consult the DG2020 user’s manual.

2. Connect two TXDATA lines of the DG2020 to J1A and J1B (TXDATA[7:0] to TXDA[7:0] and TXDB[7:0], respectively).

3. Connect two TXCT0 lines to TXCTx0 (x = A and B). Ground TXCTx1 on J2x by placing a shunt across the two pins of row 1

(TXCTx1).

4. Connect the REFCLK line of the DG2020 to REFCLKA+ (J12A) and connect REFCLK50 to REFCLKB+ (J12B). Make sure

the oscillators (Y1A and Y1B) are disconnected. This test is using the single-ended SMA clock option for both channels (see

Section 6.4 on page 18).

5. Connect the Logic Analyzer TDA700 to read the receive data lines on J5x (x= A and B) for RXDx[7:0] and on J6x for RXSTx[2:0].

6. Connect two clock inputs of the logic analyzer to RXCLKx+ (x = A and B) on J17x. The clocking of the logic analyzer needs

to be set to external. On the TDA700 series logic analyzer, go to the “SET-UP” window. After selecting external clocking, press

Figure 7-8. Generated Clock, Data and Control Signals for Encoded Mode from DG2020

[7:0]

TXDATA

REFCLK

(100 MHz.)

TXCT0

REFCLK50

00 01 55FE BF02 04 FF AA08 5510 FD20 DF40 AA

0000 FFFB 7FF7 EF

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Cypress Semiconductor CYV15G0404DXB Podręcznik Użytkownika Strona 24