
CYV15G0404DXB Evaluation Board
Users Guide
Page 27 of 56
The following steps are done for result verification on channels C and D:
1. For channel C, after the logic analyzer has acquired the data, it will pause and display the data received. Compare the data
with the transmitted data.The data should be same as the transmitted data.
2. For channel D, verify on the analyzer that the eye diagram looks as shown in Figure 7-3 on page 21. Make sure that the eye
width is 1-bit period
7.3 Reclocker Test Mode
7.3.1 Equipment Required
Equipment needed:
• CYV15G0404DXB evaluation board
• Instrument grade power supply 3-amp current limit @ 3.3V
• Oscilloscope (500 MHz or better).
• Pulse generator (20–150 MHz)
Cables needed:
• SMA to SMA coaxial cables
• Power supply cables (banana plug cables).
Table 7-6. Device Control Latch Configuration for Parallel Data Test Mode, Unencoded
ADDR Ch Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value
6
(0110b)
CSRFMODE
C[1] = ‘1’
RFMODE
C[0] =’0
FRAMCHAR
C = ‘1’
DECMODE
C = ‘1’
DECBYP
C = ‘O’
RXCKSEL
C = ‘1’
RXRATE
C = ‘0’
GLEN6
= ‘1’
10111111
7
(0111b)
CS
SDASEL2
C[1] = ‘1’
SDASEL2
C[0] = ‘0’
SDASEL1
C[1] = ‘1’
SDASEL1
C[0] = ‘0’
ENCBYP
C = ‘0’
TXCKSEL
C = ‘1’
TXRATE
C =’0’
GLEN7
= ‘1’
10101101
8
(1000b)
CD
RFEN
C = ‘1’
RXPLLPD
C = ‘1’
RXBIST
C = ‘1’
TXBIST
C = ‘1’
OE2
C = ‘1’
OE1
C = ‘1’
PABRST
C = ‘0’
GLEN8
= ‘1’
10110011
9
(1001b)
DS
RFMODE
D[1] = ‘1’
RFMODE
D[0] =’0
FRAMCHAR
D = ‘1’
DECMODE
D = ‘1’
DECBYP
D = ‘0’
RXCKSEL
D = ‘1’
RXRATE
D = ‘0’
GLEN9
= ‘1’
10111111
10
(1010b)
DS
SDASEL2
D[1] = ‘1’
SDASEL2
D[0] = ‘0’
SDASEL1
D[1] = ‘1’
SDASEL1
D[0] = ‘0’
ENCBYP
D = ‘0’
TXCKSEL
D = ‘1’
TXRATE
D =’0’
GLEN10
= ‘1’
10101101
11
(1011b)
DD
RFEN
D = ‘1’
RXPLLPD
D = ‘1’
RXBIST
D = ‘1’
TXBIST
D = ‘1’
OE2
D = ‘1’
OE1
D = ‘1’
PABRST
D = ‘0’
GLEN11
= ‘1’
10110011
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