Document Number: 001-52469 Rev. *H Page 34 of 50
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C T
A
85 °C, 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
AC Programming Specifications
Tab le 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C T
A
85 °C, 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and
are for design guidance only.
Table 29. 5 V AC External Clock Specifications
Symbol Description Min Typ Max Units
F
OSCEXT
Frequency 0.093 –24.6MHz
– High period 20.6
– 5300 ns
– Low period 20.6 – –ns
– Power-up IMO to switch 150
– – s
Notes
19. Maximum CPU frequency is 12 MHz nominal at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
20. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
21. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Table 30. 3.3 V AC External Clock Specifications
Symbol Description Min Typ Max Units
F
OSCEXT
Frequency with CPU clock divide by 1
[19]
0.093 –12.3MHz
F
OSCEXT
Frequency with CPU clock divide by 2 or greater
[20]
0.186 –24.6MHz
– High period with CPU clock divide by 1 41.7
– 5300 ns
– Low period with CPU clock divide by 1 41.7
– –ns
– Power-up IMO to switch 150 – – s
Table 31. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
t
RSCLK
Rise time of SCLK 1 – 20 ns
t
FSCLK
Fall time of SCLK 1 – 20 ns
t
SSCLK
Data setup time to falling edge of SCLK 40 – – ns
t
HSCLK
Data hold time from falling edge of SCLK 40 – – ns
F
SCLK
Frequency of SCLK 0 – 8 MHz
t
ERASEB
Flash erase time per block – 20 80
[21]
ms
t
WRITE
Flash block write time – 80 320
[21]
ms
t
DSCLK
Data out delay from falling edge of SCLK – – 45 ns V
DD
3.6
t
DSCLK3
Data out delay from falling edge of SCLK – – 50 ns 3.0 V
DD
3.6
t
ERASEALL
Flash erase time (bulk) – 20 – ms Erase all blocks and
protection fields at
once
t
PRGH
Total flash block program time
(t
ERASEB
+ t
WRITE
), hot
– – 200
[21]
ms T
J
0°C
t
PRGC
Total flash block program time
(t
ERASEB
+ t
WRITE
), cold
– – 400
[21]
ms T
J
0°C
(28 strony)
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