Cypress Semiconductor CY7C1364C Instrukcja Użytkownika

CY7C1364C9-Mbit (256 K × 32) Pipelined Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Documen

CY7C1364CDocument Number: 001-74592 Rev. *B Page 10 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1364C incorporates a serial boundary scan tes

CY7C1364CDocument Number: 001-74592 Rev. *B Page 11 of 29The TAP controller used in this SRAM is not fully compliant to the1149.1 convention because

CY7C1364CDocument Number: 001-74592 Rev. *B Page 12 of 29TAP Controller State DiagramThe 0/1 next to each state represents the value of TMS at the ri

CY7C1364CDocument Number: 001-74592 Rev. *B Page 13 of 29TAP Controller Block DiagramTAP TimingBypass Register0Instruction Register012Identication R

CY7C1364CDocument Number: 001-74592 Rev. *B Page 14 of 293.3 V TAP AC Test ConditionsInput pulse levels ...

CY7C1364CDocument Number: 001-74592 Rev. *B Page 15 of 29TAP DC Electrical Characteristics and Operating Conditions(0 °C < TA < +70 °C; VDD = 3

CY7C1364CDocument Number: 001-74592 Rev. *B Page 16 of 29Instruction CodesInstruction Code DescriptionEXTEST 000 Captures I/O ring contents. Places t

CY7C1364CDocument Number: 001-74592 Rev. *B Page 17 of 29Boundary Scan Order165-ball FBGACY7C1364C (256 K × 32) Bit# Ball ID Signal Name Bit# Ball ID

CY7C1364CDocument Number: 001-74592 Rev. *B Page 18 of 29Maximum RatingsExceeding maximum ratings may impair the useful life of thedevice. User guide

CY7C1364CDocument Number: 001-74592 Rev. *B Page 19 of 29ISB3Automatic CE Power-down Current – CMOS InputsVDD = Max., Device Deselected, VIN  0.3 V

CY7C1364CDocument Number: 001-74592 Rev. *B Page 2 of 29Logic Block Diagram – CY7C1364CADDRESSREGISTERADVCLKBURSTCOUNTER ANDLOGICCLRQ1Q0ADSPADSCMODEB

CY7C1364CDocument Number: 001-74592 Rev. *B Page 20 of 29Switching CharacteristicsOver the Operating RangeParameter [15, 16]Description-166UnitMin Ma

CY7C1364CDocument Number: 001-74592 Rev. *B Page 21 of 29Switching WaveformsFigure 3. Read Cycle Timing [21]tCYCtCLCLKADSPtADHtADSADDRESStCHOEADSCCE

CY7C1364CDocument Number: 001-74592 Rev. *B Page 22 of 29Figure 4. Write Cycle Timing [22, 23]Switching Waveforms (continued)tCYCtCLCLKADSPtADHtADSA

CY7C1364CDocument Number: 001-74592 Rev. *B Page 23 of 29Figure 5. Read/Write Cycle Timing [24, 25, 26]Switching Waveforms (continued)tCYCtCLCLKADSP

CY7C1364CDocument Number: 001-74592 Rev. *B Page 24 of 29Figure 6. ZZ Mode Timing [27, 28]Switching Waveforms (continued)tZZISUPPLYCLKZZtZZRECALL IN

CY7C1364CDocument Number: 001-74592 Rev. *B Page 25 of 29Ordering InformationNot all of the speed, package and temperature ranges are available. Plea

CY7C1364CDocument Number: 001-74592 Rev. *B Page 26 of 29Package DiagramFigure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter)

CY7C1364CDocument Number: 001-74592 Rev. *B Page 27 of 29Acronyms Document ConventionsUnits of MeasureAcronym DescriptionCEchip enableCMOS complement

CY7C1364CDocument Number: 001-74592 Rev. *B Page 28 of 29Document History PageDocument Title: CY7C1364C, 9-Mbit (256 K × 32) Pipelined Sync SRAMDocum

Document Number: 001-74592 Rev. *B Revised February 28, 2012 Page 29 of 29i486 is a trademark, and Intel and Pentium are registered trademarks, of In

CY7C1364CDocument Number: 001-74592 Rev. *B Page 3 of 29ContentsPin Configurations ...4Pin D

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Cypress Semiconductor: CY7

CY7C1364CDocument Number: 001-74592 Rev. *B Page 4 of 29Pin ConfigurationsFigure 1. 165-ball FBGA (15 × 17 × 1.40 mm) pinoutCY7C1364C (256 K × 32)23

CY7C1364CDocument Number: 001-74592 Rev. *B Page 5 of 29Pin DefinitionsName I/O DescriptionA0, A1, A Input-SynchronousAddress Inputs used to select o

CY7C1364CDocument Number: 001-74592 Rev. *B Page 6 of 29Functional OverviewAll synchronous inputs pass through input registers controlled bythe risin

CY7C1364CDocument Number: 001-74592 Rev. *B Page 7 of 29safety precaution, DQs are automatically tri-stated whenever aWrite cycle is detected, regard

CY7C1364CDocument Number: 001-74592 Rev. *B Page 8 of 29Truth TableThe truth table for CY7C1364C follows. [1, 2, 3, 4, 5]Next Cycle Address Used ZZ C

CY7C1364CDocument Number: 001-74592 Rev. *B Page 9 of 29Truth Table for Read/WriteThe Truth Table for Read/Write for CY7C1364C follows. [6, 7]Functio