Cypress Semiconductor CYDC128B16 Instrukcja Użytkownika Pobierz pdf (Strona 23)

CYDC128B16

Document #: 001-01638 Rev. *H Page 23 of 29

Figure 12. Busy Timing Diagram No.1 (CE Arbitration)

Figure 13. Busy Timing Diagram No.2 (Address Arbitration)

[24]

Note

24. If t

is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Switching Waveforms (continued)

ADDRESS MATCH

BLC

BHC

ADDRESS MATCH

BLC

BHC

Valid First

ADDRESS

L,R

BUSY

ADDRESS

L,R

Valid First

[24]

ADDRESS MATCH

ADDRESS

BUSY

ADDRESS MISMATCH

or t

BLA

BHA

ADDRESS

ADDRESS MATCH ADDRESS MISMATCH

ADDRESS

BUSY

or t

BLA

BHA

ADDRESS

Right Address Valid First

Left Address Valid First

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