Cypress Semiconductor CY7C1364C Instrukcja Użytkownika Pobierz pdf (Strona 15)

CY7C1364C

Document Number: 001-74592 Rev. *B Page 15 of 29

TAP DC Electrical Characteristics and Operating Conditions

(0 °C < T

< +70 °C; V

= 3.3 V ± 0.165 V unless otherwise noted)

Parameter

[10]

Description Conditions Min Max Unit

OH1

Output HIGH voltage I

= –4.0 mA V

DDQ

= 3.3 V 2.4 – V

= –1.0 mA V

DDQ

= 2.5 V 2.0 – V

OH2

Output HIGH voltage I

= –100 µA V

DDQ

= 3.3 V 2.9 – V

DDQ

= 2.5 V 2.1 – V

OL1

Output LOW voltage I

= 8.0 mA V

DDQ

= 3.3 V – 0.4 V

= 8.0 mA V

DDQ

= 2.5 V – 0.4 V

OL2

Output LOW voltage I

= 100 µA V

DDQ

= 3.3 V – 0.2 V

DDQ

= 2.5 V – 0.2 V

Input HIGH voltage V

DDQ

= 3.3 V 2.0 V

+ 0.3 V

DDQ

= 2.5 V 1.7 V

+ 0.3 V

Input LOW voltage V

DDQ

= 3.3 V –0.5 0.7 V

DDQ

= 2.5 V –0.3 0.7 V

Input load current GND < V

< V

DDQ

–5 5 µA

Identification Register Definitions

Instruction Field CY7C1364C (256 K × 32) Description

Revision number (31:29) 000 Describes the version number

Device depth (28:24)

[11]

01011 Reserved for internal use

Device width (23:18) 165-ball FBGA 000000 Defines memory type and architecture

Cypress device ID (17:12) 011110 Defines width and density

Cypress JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor

ID register presence indicator (0) 1 Indicates the presence of an ID register

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary scan order (165-ball FBGA package) 71

Notes

10. All voltages referenced to V

(GND)

11. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 29 30

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