Cypress Semiconductor CY7C1356CV25 Instrukcja Użytkownika Pobierz pdf (Strona 13)

CY7C1354CV25

CY7C1356CV25

Document #: 38-05537 Rev. *H Page 12 of 28

TAP Timing

TAP AC Switching Characteristics

Over the Operating Range

[11, 12]

Parameter Description Min. Max. Unit

Clock

TCYC

TCK Clock Cycle Time 50 ns

TCK Clock Frequency 20 MHz

TCK Clock HIGH Time 20 ns

TCK Clock LOW Time 20 ns

Output Times

TDOV

TCK Clock LOW to TDO Valid 10 ns

TDOX

TCK Clock LOW to TDO Invalid 0 ns

Set-up Times

TMSS

TMS Set-up to TCK Clock Rise 5 ns

TDIS

TDI Set-up to TCK Clock Rise 5 ns

Capture Set-up to TCK Rise 5 ns

Hold Times

TMSH

TMS Hold after TCK Clock Rise 5 ns

TDIH

TDI Hold after Clock Rise 5 ns

Capture Hold after Clock Rise 5 ns

Notes:

11. t

and t

refer to the set-up and hold time requirements of latching data from the boundary scan register.

12. Test conditions are specified using the load in TAP AC test Conditions. t

= 1 ns.

Test Clock

(TCK)

123456

est Mode Select

(TMS)

Test Data-Out

(TDO)

CYC

Test Data-In

(TDI)

TMSH

TMSS

TDIH

TDIS

TDOX

TDOV

DON’T CARE UNDEFINED

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 28 29

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