Cypress Semiconductor CY7C1380C Instrukcja Użytkownika Pobierz pdf (Strona 7)

PRELIMINARY

CY7C1380C

CY7C1382C

Document #: 38-05237 Rev. *B Page 7 of 28

Introduction

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (t

) is 2.6 ns

(250-MHz device).

The CY7C1380C/CY7C1382C supports secondary cache in

systems utilizing either a linear or interleaved burst sequence.

The interleaved burst order supports Pentium

and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP

) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV

input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE

) and Byte Write Select (BW

a,b,c,d

for CY7C1380 and

a,b

for CY7C1382) inputs. A Global Write Enable (GW)

overrides all byte write inputs and writes data to all four bytes.

All writes are simplified with on-chip synchronous self-timed

write circuitry.

Synchronous Chip Selects (CE

, CE

for TQFP/CE

for

BGA) and an asynchronous Output Enable (OE

) provide for

easy bank selection and output three-state control. ADSP is

ignored if CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP

or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW

, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE

is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP

or ADSC signals, its output will three-state

immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP

is asserted LOW, and (2)

chip select is asserted active. The address presented is

loaded into the address register and the address

advancement logic while being delivered to the RAM core. The

write signals (GW

, BWE, and BWx) and ADV inputs are

ignored during this first cycle.

ADSP

triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the RAM core. If GW

is HIGH,

then the write operation is controlled by BWE and BWx

signals. The CY7C1380C/CY7C1382C provides byte write

capability that is described in the Write Cycle Description table.

Asserting the Byte Write Enable input (BWE

) with the selected

Byte Write (BW

a,b,c,d

for CY7C1380C and BW

a,b

for

CY7C1382C) input will selectively write to only the desired

bytes. Bytes not selected during a byte write operation will

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

Because the CY7C1380C/CY7C1382C is a common I/O

device, the Output Enable (OE

) must be deasserted HIGH

before presenting data to the DQ

inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ are

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and (4)

the appropriate combination of the write inputs (GW

, BWE,

and BWx) are asserted active to conduct a write to the desired

byte(s). ADSC

triggered write accesses require a single clock

cycle to complete. The address presented to A

[17:0]

is loaded

into the address register and the address advancement logic

while being delivered to the RAM core. The ADV

input is

TCK JTAG serial clock Serial clock to the JTAG circuit. (BGA and FBGA Only)

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V –5% +10%

power supply.

Ground Ground for the core of the device. Should be connected to ground of the system.

DDQ

I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.5 –5% to 3.3V +10% power supply.

SSQ

I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.

36M

72M

144M

– No connects. Reserved for address expansion. Pins are not internally connected.

NC – No connects. Pins are not internally connected.

Pin Definitions

Name I/O Description

1 2 3 4 5 6 7 8 9 10 11 12 ... 27 28

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