
PRELIMINARY
CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *B Page 21 of 28
Read/Write Cycle Timing
[4, 18, 19, 20, 21]
Switching Waveforms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE
1
OE
GW
WE
CE
2
CE
3
1a
Data In/Out
t
CYC
t
CH
t
CL
t
ADS
t
ADH
t
ADVS
t
ADVH
RD1
WD2
WD3
t
AH
t
AS
t
WS
t
WH
t
WH
t
WS
t
CES
t
CEH
t
CES t
CEH
t
CES
t
CEH
t
EOLZ
t
CO
t
EOV
4a
4c
4d
1a
t
EOHZ
t
DOH
t
CHZ
Single Read
Burst Read
= DON’T CARE
= UNDEFINED
Pipelined Read
Out
2a
In
4b
Out
Out
Out
Out
Single Write
t
DS
t
DH
Single Write
RD4
RD5
Single cycle
deselect
I/O Disabled within one clock
cycle after deselect
3a
In
CE
1
Unselected
Komentarze do niniejszej Instrukcji