Cypress Semiconductor CY7B991 Instrukcja Użytkownika Pobierz pdf (Strona 12)

CY7B991

CY7B992

Figure 8

shows the CY7B991/992 connected in series to con-

struct a zero-skew clock distribution tree between boards. De-

lays of the downstream clock buffers can be programmed to

compensate for the wire length (i.e., select negative skew

equal to the wire delay) necessary to connect them to the mas-

ter clock source, approximating a zero-delay clock tree. Cas-

caded clock buffers will accumulate low-frequency jitter be-

cause of the non-ideal filtering characteristics of the PLL filter.

It is recommended that not more than two clock buffers be

connected in series.

Figure 7. Multi-Function Clock Driver

Figure 8. Board-to-Board Clock Distribution

20–MHz

DISTRIBUTION

CLOCK

80-MHz

INVERTED

7B991–14

20-MHz

80-MHz

ZERO SKEW

80-MHz

SKEWED –3.125 ns (–4t

)

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

TEST

REF

LOAD

SYSTEM

CLOCK

7B991–15

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

TEST

REF

4F0

4F1

3F0

3F1

2F0

2F1

1F0

1F1

4Q0

4Q1

3Q0

3Q1

2Q0

2Q1

1Q0

1Q1

REF

LOAD

TEST

1 2 ... 7 8 9 10 11 12 13 14

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Cypress Semiconductor CY7B991 Instrukcja Użytkownika Strona 12

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