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Cypress Semiconductor MoBL CY62157EV30 Instrukcja Użytkownika Strona 1

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CY62157EV30 MoBL
®
8 Mbit (512K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05445 Rev. *H Revised December 20, 2010
Features
■ Thin small outline package (TSOP) I package configurable as
512K x 16 or 1M x 8 static RAM (SRAM)
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
❐ Automotive-E: –40°C to +125°C
■ Wide voltage range: 2.20V to 3.60V
■ Pin compatible with CY62157DV30
■ Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A (Industrial)
■ Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■ Easy memory expansion with CE
1
, CE
2
, and OE features
■ Automatic power down when deselected
■ Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free and non Pb-free 48-Ball very fine ball grid
array (VFBGA), Pb-free 44-Pin TSOP II and 48-Pin TSOP I
packages
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE
1
HIGH or CE
2
LOW or
both BHE
and BLE are HIGH). The input or output pins (I/O
0
through I/O
15
) are placed in a high impedance state when the
device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are
disabled (OE
HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE
, BLE HIGH), or a write operation is active (CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE
) inputs LOW. If Byte Low Enable
(BLE
) is LOW, then data from I/O pins (I/O
0
through I/O
7
) is
written into the location specified on the address pins (A
0
through
A
18
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE
) LOW while forcing the Write
Enable (WE
) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O
8
to I/O
15
. See the Truth Table on page
11 for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
512K × 16/1M x 8
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
Power Down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
BYTE
Logic Block Diagram
[+] Feedback
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Podsumowanie treści

Strona 1 - 8 Mbit (512K x 16) Static RAM

CY62157EV30 MoBL®8 Mbit (512K x 16) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document

Strona 2

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 10 of 17Figure 10 shows WE Controlled, OE LOW write cycle waveforms.[27]Figure 10. Write Cycle N

Strona 3

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 11 of 17 Truth TableCE1CE2WE OE BHE BLE Inputs/Outputs Mode PowerH X[29]X X X X High-Z Deselect/p

Strona 4

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 12 of 17Ordering InformationSpeed(ns) Ordering CodePackageDiagramPackage TypeOperatingRange45 CY6

Strona 5

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 13 of 17Package DiagramsFigure 12. 48-Pin VFBGA (6 x 8 x 1 mm), 51-8515051-85150-*E[+] Feedback

Strona 6

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 14 of 17Figure 13. 44-Pin TSOP II, 51-85087Package Diagrams (continued)MAXMIN.DIMENSION IN MM (I

Strona 7

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 15 of 17Figure 14. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183Package Diagrams (continued

Strona 8

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 16 of 17Document History PageDocument Title: CY62157EV30 MoBL®, 8 Mbit (512K x 16) Static RAMDocu

Strona 9

Document #: 38-05445 Rev. *H Revised December 20, 2010 Page 17 of 17MoBL is a registered trademark and More Battery Life is a trademark of Cypress Se

Strona 10 - CY62157EV30 MoBL

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 2 of 17ContentsPin Configuration ...3P

Strona 11

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 3 of 17Pin ConfigurationFigure 1. 48-Ball VFBGA (Top View) [2]Figure 2. 44-Pin TSOP II (Top Vie

Strona 12

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 4 of 17Maximum RatingsExceeding the maximum ratings may impair the useful life of the device. Use

Strona 13

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 5 of 17CapacitanceTested initially and after any design or process changes that may affect these

Strona 14

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 6 of 17Data Retention Characteristics Over the Operating RangeParameter Description Conditions Mi

Strona 15

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 7 of 17Switching Characteristics Over the Operating Range[14, 15] Parameter Description45 ns (Ind

Strona 16

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 8 of 17Switching WaveformsFigure 6 shows Address Transition Controlled read cycle waveforms.[20,

Strona 17

CY62157EV30 MoBL®Document #: 38-05445 Rev. *H Page 9 of 17Figure 8 shows WE Controlled write cycle waveforms.[23, 24, 25]Figure 8. Write Cycle No.

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