CY7C603xx
Document #: 38-16018 Rev. *D Page 25 of 29
AC I
2
C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 3.6V
and 0°C <
T
A
< 70°C, or 2.4V to 3.0V and 0°C < T
A
< 70°C, respectively. Typical parameters apply to 3.3V, or 2.7V at 25°C and
are for design guidance only.
Table 28.AC Characteristics of the I
2
C SDA and SCL Pins for Vdd >3.0V
Parameter Description
Standard Mode Fast Mode
Unit Notes
Min. Max. Min. Max.
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0 –0.6– Ps
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3– Ps
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6– Ps
T
SUSTAI2C
Set-up Time for a Repeated START Condition 4.7 –0.6– Ps
T
HDDATI2C
Data Hold Time 0 –0– Ps
T
SUDATI2C
Data Set-up Time 250 –100
[13]
–ns
T
SUSTOI2C
Set-up Time for STOP Condition 4.0 –0.6– Ps
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7 –1.3– Ps
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter.
– –050ns
Note
13. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SU;DAT
> 250 ns must then be met. This will automatically
be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Table 29.2.7V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode not Supported)
Parameter Description
Standard Mode Fast Mode
Unit Notes
Min. Max. Min. Max.
F
SCLI2C
SCL Clock Frequency 0 100 – – kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0 – – – Ps
T
LOWI2C
LOW Period of the SCL Clock 4.7 – – – Ps
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 – – – Ps
T
SUSTAI2C
Set-up Time for a Repeated START Condition 4.7 – – – Ps
T
HDDATI2C
Data Hold Time 0 – – – Ps
T
SUDATI2C
Data Set-up Time 250 – – –ns
T
SUSTOI2C
Set-up Time for STOP Condition 4.0 – – – Ps
T
BUFI2C
Bus Free Time Between a STOP and START
Condition
4.7 ––– Ps
T
SPI2C
Pulse Width of spikes are suppressed by the
input filter.
– –––ns
(94 strony)
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