
Document Number: 38-02009 Rev. *K Page 11 of 17
AC Specifications
Table 6. AC Specifications—Parallel Interface
Parameter Description Min Max Unit
t
TS
TXCLKI Frequency (must be frequency coherent to REFCLK) 154.5 156.5 MHz
t
TXCLKI
TXCLKI Period 6.38 6.47 ns
t
TXCLKID
TXCLKI Duty Cycle 40 60 %
t
TXCLKIR
TXCLKi Rise Time 0.3 1.5 ns
t
TXCLKIF
TXCLKi Fall Time 0.3 1.5 ns
t
TXDS
Write Data Setup to ↑ of TXCLKI 1.5 ns
t
TXDH
Write Data Hold from ↑ of TXCLKI 0.5 ns
t
TOS
TXCLKO Frequency 154.5 156.5 MHz
t
TXCLKO
TXCLKO Period 6.38 6.47 ns
t
TXCLKOD
TXCLKO Duty Cycle 43 57 %
t
TXCLKOR
TXCLKO Rise Time 0.3 1.5 ns
t
TXCLKOF
TXCLKO Fall Time 0.3 1.5 ns
t
RS
RXCLK Frequency 154.5 156.5 MHz
t
RXCLK
RXCLK Period 6.38 6.47 ns
t
RXCLKD
RXCLK Duty Cycle 43 57 %
t
RXCLKR
RXCLK Rise Time
[6]
0.3 1.5 ns
t
RXCLKF
RXCLK Fall Time
[6]
0.3 1.5 ns
t
RXDS
Recovered Data Setup with reference to ↑ of RXCLK 2.2 ns
t
RXDH
Recovered Data Hold with reference to ↑
of RXCLK 2.2 ns
t
RXPD
Valid Propagation Delay –1.0 1.0 ns
Table 7. AC Specifications—REFCLK
The AC Specifications—REFCLK follow.
[7]
Parameter Description Min Max Unit
t
REF
REFCLK Input Frequency 154.5 156.5 MHz
t
REFP
REFCLK Period 6.38 6.47 ns
t
REFD
REFCLK Duty Cycle 35 65 %
t
REFT
REFCLK Frequency Tolerance — (relative to received serial data)
[8]
–100 +100 ppm
t
REFR
REFCLK Rise Time 0.3 1.5 ns
t
REFF
REFCLK Fall Time 0.3 1.5 ns
Table 8. AC Specifications–CML Serial Outputs
Parameter Description Min Typical Max Unit
t
RISE
CML Output Rise Time (20–80%, 100Ω balanced load) 60 170 ps
t
FALL
CML Output Fall Time (80–20%, 100Ω balanced load) 60 170 ps
Notes
6. RXCLk rise time and fall times are measured at the 20 to 80 percentile region of the rising and falling edge of the clock signal.
7. The 155.52 MHz Reference Clock Phase Noise Limits for the CYS25G0101DX are shown in Figure 6.
8. +20 ppm is required to meet the SONET output frequency specification.
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