Cypress Semiconductor CY7C1365C Instrukcja Użytkownika Pobierz pdf (Strona 27)

CY7C1361V25

CY7C1363V25

CY7C1365V25

PRELIMINARY

27

Notes:

19. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device.

20. I/Os are in three-state when exiting ZZ sleep mode.

Timing Diagrams

(continued)

ADSP

CLK

ADSC

CE

1

CE

3

LOW

HIGH

ZZ

t

ZZS

t

ZZREC

I

CC

I

CC

(active)

Three-state

I/Os

ZZ Mode Timing

[19, 20]

CE

2

I

CCZZ

HIGH

1 2 ... 22 23 24 25 26 27 28 29 30

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