Cypress Semiconductor CY7C1364C Instrukcja Użytkownika Pobierz pdf (Strona 9)

CY7C1360V25

CY7C1362V25

CY7C1364V25

PRELIMINARY

Asserting ADV

LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

, CE

, ADSP, and ADSC must remain inactive for the

duration of t

ZZREC

after the ZZ input returns LOW.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]]

[1:0]

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

[1:0]

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

DDZZ

Snooze mode

standby current

ZZ > V

− 0.2V 15 mA

ZZS

Device operation to

ZZ > V

− 0.2V 2t

CYC

ZZREC

ZZ recovery time ZZ < 0.2V 2t

CYC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 30 31

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