CY7C1360V25
CY7C1362V25
CY7C1364V25
PRELIMINARY
4
Selection Guide
7C1360V25-200
7C1364V25-200
7C1362V25-200
7C1360V25-166
7C1364V25-166
7C1362V25-166
7C1360V25-133
7C1364V25-133
7C1362V25-133
7C1360V25-100
7C1364V25-100
7C1362V25-100
Maximum Access Time (ns) 3.1 3.5 4.0 5.0
Maximum Operating Current (mA) Commercial 450 400 350 325
Maximum CMOS Standby Current (mA) 10 10 10 10
Pin Definitions (100-Pin TQFP)
x18 Pin Locations x36 Pin Locations Name I/O Description
37, 36, 32–25,
43–50, 80–82, 99,
100
37, 36, 32–35,
43–50, 81, 82, 99,
100
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address
locations. Sampled at the rising edge of the CLK if
ADSP
or ADSC is active LOW, and CE
1
, CE
2
, and
CE
3
are sampled active. A
[1:0]
feed the 2-bit
counter.
93, 94 93, 94, 95, 96, BW
a
BW
b
BW
c
BW
d
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with
BWE
to conduct byte writes to the SRAM. Sampled
on the rising edge of CLK.
88 88 GW Input-
Synchronous
Global Write Enable Input, active LOW. When as-
serted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regard-
less of the values on BW
a,b,c,d
and BWE).
87 87 BWE Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on
the rising edge of CLK. This signal must be assert-
ed LOW to conduct a byte write.
89 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs
to the device. Also used to increment the burst
counter when ADV
is asserted LOW, during a burst
operation.
98 98 CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select/deselect the device. ADSP is ig-
nored if CE
1
is HIGH.
97 97 CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select/deselect the device.
92 92 CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the
rising edge of CLK. Used in conjunction with CE
1
and
CE
2
to select/deselect the device.
86 86 OE Input-
Asynchronous
Output Enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input
data pins. OE
is masked during the first clock of a
read cycle when emerging from a deselected state.
83 83 ADV Input-
Synchronous
Advance Input signal, sampled on the rising edge
of CLK. When asserted, it automatically increments
the address in a burst cycle.
84 84 ADSP Input-
Synchronous
Address Strobe from Processor, sampled on the
rising edge of CLK. When asserted LOW, A is cap-
tured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP
and ADSC are
both asserted, only ADSP
is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
(53 strony)
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