Cypress Semiconductor FX2LP Przewodnik Instalacji Pobierz pdf (Strona 11)

EZ-USB Development Board Page -7

4.3 Jumpers

4.4 EEPROM Select & Enable Switches SW1 and SW2

SW1 selects between two socketed EEPROMS, one strapped to address 000 (U6), and the other

strapped to address 001(U5).

SW2 enables or disables the EEPROM selected by SW1.

The EZ-USB chip has various start-up modes, which depend on the existence of an EEPROM

connected to its SCL and SDA lines. Switches SW1 and SW2 allow the EEPROMS to be “discon-

nected” from FX2, or to be connected using one of two EEPROMS installed in sockets U5 and U6.

The EZ-USB chip contains two I

C controllers, a “boot load” controller, and an 8051 controller.

The boot load controller operates when EZ-USB comes out of reset, and the 8051 controller oper-

ates under firmware control once the 8051 is running, permitting the 8051 to access general- pur-

pose I

C devices connected to the SCL and SDA lines. The discussion below deals with the roles

of SW1 and SW2 in accommodating the various boot load mechanisms.

The EZ-USB boot loader accommodates two EEPROM types, in “Small” and “Large” versions, as

shown by Table 2.

Table 1. EZ-USB Development Board Jumpers

Jumper Function Default Notes

JP1 Connects 3.3 volt

power to the EZ-USB

chip.

(1-2)

JP2 Powers the on-board

3.3 volt regulator from

USB Vbus pin

(1-2)

To operate the board in self-powered mode, remove JP2 and

supply 4-5V to JP2-1, and GND to a ground pin (TP1 is a

convenient GND point).

JP3 Connects four GAL

pins to LEDS D2, D3,

D4, D5

(1-2)

(3-4)

(5-6)

(7-8)

U2, the on-board GAL, contains code to use the four LEDs

as software settable indicators. If you wish to (a) use the

GAL pins for something else, which requires re-programming

the GAL or (b) wire the general purpose indicators D2-D5 to

other parts of the board, first remove the appropriate shorting

plug(s).

JP5 3.3 Volt Power IN

(1-2)

Supplies 3.3 volt power to the board. It may be removed and

replaced with ammeter probes in series to measure board

current.

JP6

JP7

Memory map selec-

tion

OUT

(1-2)

These jumpers select one of four memory maps for U3, the

external 128 Kilobyte RAM. See the Memory Map section

for details.

JP8 Wakeup2 Pin OUT

(1-2)

Inserting a shorting plug into JP8 connects an on-board RC

network (R42,C43) to the secondary remote wakeup pin

WU2. This R-C network can be used to test periodic remote

wakeup firmware when this dual-purpose pin (it defaults to

PA3) is programmed as WU2.

JP9 I2C bus test points n/a The I2C bus SCL and SDA lines may be monitored or exter-

nally connected using JP9.

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 27 28

Komentarze do niniejszej Instrukcji

Brak uwag

Cypress Semiconductor FX2LP Przewodnik Instalacji Strona 11

Komentarze do niniejszej Instrukcji

Powiązane produkty i podręczniki dla Networking Cypress Semiconductor FX2LP