Cypress Semiconductor enCoRe CY7C64215 Instrukcja Użytkownika Pobierz pdf (Strona 9)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

USB Bootloader

enCoRe III supports in-system programmability. This, how-

ever, requires that the chip follow serial programming proto-

col during programming (the programming protocol is not

USB). A 5-pin header on the system board is also required

for in-system programming.

Bootloaders are programs that reside in the device memory.

These programs make it possible to download user code to

the chip using USB protocol. The memory containing the

bootloader code should be protected to prevent it from being

changed or written to. This requires only an application on the

host and bootloader firmware on the device. At the time of

writing this application note, there are plans to include the

USB bootloader as a user module in the PSoC Designer

tool.[1]

SROM

The SROM holds code that is used to boot the PSoC device,

calibrate circuitry, and perform Flash operations. The func-

tions provided by the SROM are called from code stored in

the Flash or by device programmers. The SROM is used to

provide interface functions to the Flash banks. The SROM

functions are accessed by executing the Supervisory System

Call instruction (SSC), which has an opcode of 00h. Prior to

executing the SSC, the M8C’s accumulator needs to load

with the desired SROM function. Attempting to access unde-

fined functions will cause a HALT. The SROM functions exe-

cute code with calls; therefore, the functions require stack

space. The SROM functions and parameters are defined in

detail in the PSoC TRM available on www.cypress.com

Firmware Development

The CY7C64x13 is provided with a framework—code for

USB SIE operation. The framework provides for a defined

enumeration firmware. Descriptors for class devices are also

available.

The enCoRe III uses a different development system that

provides a GUI interface (with pull-down menus) called the

‘USB Setup Wizard’ to set up the enumeration firmware. Pre-

defined HID Report descriptors for a 3-button mouse and a

keyboard with LED are also provided with the tool.

The USB registers in enCoRe III include the PMA read and

write registers and the USB Start of Frame register

(USB_SOFx). The USB_SOFx register provides access to

the 11-bit SOF frame number. Due to its configurability

enCoRe III provides a large number of registers to the user.

These registers are available in two different register banks.

While porting designs from the CY7C64x13, the user must

make sure of the following as far as firmware is concerned.

■ Register locations are correct.

■ Bit locations in registers (USB bus activity bit, data valid

bit, etc.) are correct.

■ Firmware provides for changing register banks. The banks

and registers are given in the enCoRe III data sheet and

the PSoC TRM available at www.cypress.com.

Firmware porting for some of the important USB functions is

given in the following sections.

Suspend Condition

USB microcontrollers are required by specification to go into

a suspend mode when no activity is seen on the USB bus for

more than 3.0 ms. Full-speed devices must shut down the

SIE and draw only suspend current from the host while pro-

viding power to the D+ line for maintaining correct connectiv-

ity status. On the CY7C64x13 microcontroller the clock

oscillators, 12-bit timer, and watchdog timer are shut down

when the device is put into suspend. The only blocks

switched on are the USB receiver and the GPIO interrupt

logic. The run bit in the Processor Status and Control register

(Address 0xFF) should be set to resume the part out of sus-

pend. On the CY7C64215 microcontroller the only blocks that

are switched on during suspend are the 32 KHz oscillator,

blocks clocked by this oscillator, and the supply voltage mon-

itoring circuit. The analog blocks should be powered down by

firmware. The USB wakeup interrupt should be enabled to

assist resuming USB operation. Typical algorithms for enter-

ing suspend in the case of both microcontrollers are given

below:

CY7C64x13 Microcontroller

1. Monitor loss of USB activity for a specific time, e.g., 3 ms.

If no activity is detected start the suspend condition;

1ms_ISR: Check bit [3] of register [0x1F] – USB Status

and Control Register for activity every millisecond. Incre-

ment counter if there is no activity and clear if there is

activity. Check if counter reaches 3 and then start suspend

steps.

2. All GPIO set to low-power state (no floating pins).

3. Enable GPIO interrupts if desired for wake-up; Set bit [5]

of the Global Interrupt Enable Register at address [0x20].

4. Set suspend and run bits; mov A, 09h.

5. Write to Status and Control Register. Enter suspend, wait

for USB activity (or GPIO Interrupt); IOWR FFh.

6. NOP – This executes before any ISR and is prefetched by

the processor.

7. Remaining code for exiting suspend routine.

CY7C64215 Microcontroller

1. Monitor bus activity bit for a specific time, e.g., 3 ms. If no

activity is detected start the suspend condition.

2. Enable interrupts; call M8C_EnableGInt or set bit [0] of the

CPU_F register at location [F7h].

3. Call the USB_Suspend API function or write a ‘0’ to bit 7

of the USB_CR0 register. This disables USB transceiver,

but maintains the USB address; USB_CR0 &= (0x7F).

Note

1. If you require a sample USB bootloader, please create a case by going to Technical Support on www.cypress.com.

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