Cypress Semiconductor enCoRe CY7C64215 Instrukcja Użytkownika Pobierz pdf (Strona 6)

August 17, 2011 Document No. 001-15340 Rev. *A

AN6073

Figure 4. enCoRe III Stack/SRAM Setup

enCoRe III has 16 KB of FLASH, 1K SRAM for user variables

and stack. The 1K SRAM is made available using four 256-

byte blocks. The STK_PP register (location 0,D1h) uses bits

[2:0] to select the appropriate SRAM page for stack opera-

tions. The Stack wraps around from FF to 00h, so the user

must take precautions against overwriting data variables in

the RAM. The PSoC Designer tool automatically handles

RAM access through memory models (large and small) and

stack parameters. Default settings are large memory model

and single RAM (page 3) for stack and indexed memory

operations. User can modify parameters in the memory.inc

file for desired RAM access patterns.

Additionally, enCoRe III has a dedicated 256-byte RAM for

the endpoints. This dedicated SRAM cannot be accessed by

means of M8C instructions. It can only be accessed using

PMA (PSoC Memory Arbiter) registers. The PMA acts as the

interface between the M8C and SIE to avoid potential con-

flicts when accessing the same SRAM locations. When the

SIE writes data to the FIFO, the internal data bus is driven by

the SIE and not the CPU. This could lead to conflicts if the

CPU speed is greater than 12 MHz, particularly when the

value of the SysClk divider (selected in the PSoC Designer

tool) is ‘1’. In such cases, before transfer occurs the CPU

speed is brought down to 12 MHz for reliable operation. This

occurs with OUT transfers and the condition is taken into

account in the Read_OutEP API function.

Stack

The CY7C64x13 has separate program and data stacks. The

data stack grows from higher memory address to lower. The

data stack starting location can be configured by writing to the

DSP register. Firmware must set DSP to avoid memory con-

flicts with the endpoint FIFOs.

The CY7C64215 has a single stack for program and data.

The stack can be in any of the 4 SRAM banks. By default the

stack is in page 0, but can be changed using bits [2:0] in the

STK_PP register. Set the STK_PP register [2:0] value in the

beginning of the program and do not change after it has

grown. The stack wraps around from FFh to 00h. Firmware

should ensure that the stack doesn’t overlap with user

defined variables in the RAM.

Endpoints

The CY7C64x13 has 1 control endpoint and 4 data end-

points. This can be configured (the number of endpoints and

their sizes) by writing to bits 7,6 in USBCR register (0x1F).

Up to four 8-byte data endpoints or two 32-byte data end-

points are possible. The endpoint FIFOs reside in the upper

RAM locations. The unused RAM locations are used for data

variables.

The CY7C64215 also has 1 control and 4 data endpoints. It

has a dedicated 256-byte buffer for the endpoints in addition

to user RAM. This 256-byte buffer can be configured to be

shared between the 4 data endpoints. The development tool,

PSoC Designer by default, configures each of the 4 end-

points with 64 bytes each. This setting can be manually

changed to suit the designer’s needs.

CPU Registers

An important difference between the two microcontrollers that

must be accounted for is the location of CPU registers. Most

of the registers in the CY7C64x13 and the CY7C64215 are

present in different locations. In addition, some of the regis-

ters for HAPI and DAC control are not present in the

enCoRe III. Almost all USB registers in the CY7C64x13 have

an equivalent in the enCoRe III. One main difference

between CPU registers in the microcontrollers is that

enCoRe III has 512 8-bit registers that come in 2

banks—Bank0 and Bank1. When writing to a register the

user must also account for its bank. Bank0 is the default. Bit

4, XIO in the CPU_F register (located at F7h) must be set to

access the upper 256 registers. There are also system mac-

ros provided for this—SetBank0 and SetBank1 in the devel-

opment tool. The CPU_F register can be accessed (read or

written) no matter what bank is used.

Interrupts

In the CY7C64x13 microcontroller, the first lower 26 bytes of

PROM are dedicated for 13 interrupt vectors. Some of the

interrupts available are USB bus reset, 128-μs, 1-ms, USB

endpoints interrupts, DAC, GPIO, and I2C interrupt in that

order from the lower ROM address location. The lower-num-

ber interrupts have the highest priority. Interrupt latency is

based on time for current instruction, time to change program

counter to interrupt address (13 cycles), and time for LJMP

instruction to execute (7 cycles).

Address

0x000/

0x100/

0x200/

0x300

Address

0x0FF/

0x1FF/

0x2FF/

0x3FF

Stack begins at 0x000/

0x100/0x200/0x300

and grows upwards

Top of RAM page

Page 1

SRAM

256

Bytes

00h

FFh

Page 0

SRAM

256

Bytes

Page 3

SRAM

256

Bytes

Page 2

SRAM

256

Bytes

Stack

wraps

around

from

xFFh to

x00h

1 2 3 4 5 6 7 8 9 10 11 ... 15 16

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