CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 34 of 62
GPIO Port Configuration
All the GPIO configuration registers have common configu-
ration controls. The following are the bit definitions of the GPIO
configuration registers. By default all GPIOs are configured as
inputs. In order to prevent the inputs from floating the pull up
resistors are enabled. Firmware will need to configure each of
the GPIOs prior to use.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the
pin is configured for input or output. All interrupts are edge
sensitive, however for any interrupt that is shared by multiple
sources (i.e., Ports 2, 3, and 4) all inputs must be deasserted
before a new interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the
interrupt on the pin and then to generate the interrupt by
driving the appropriate pin state. This is useful in test and may
find value in applications as well.
Int Act Low
When clear, the corresponding interrupt is active HIGH. When
set, the interrupt is active LOW. For P0.2–P0.4 Int act Low
causes interrupts to be active on the rising edge. Int act Low
set causes interrupts to be active on the falling edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input
has standard CMOS threshold.
Important Note: The GPIOs default to CMOS threshold.
User’s firmware needs to configure the threshold to TTL mode
if necessary.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have
50-mA sink drive capability. Other pins have 8-mA sink drive
capability.
On the CY7C602xx, only the P1.7–P1.3 have 50-mA sink drive
capability. Other pins have 8-mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is
set, the pin is in high impedance state. If the corresponding bit
in the Port Data Register is clear, the pin is driven LOW.
When clear, the output is driven LOW or HIGH.
Pull Up Enable
When set the pin has a 7K pull up to V
DD
.
When clear, the pull- up is disabled.
Output Enable
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
P0.0(CLKIN) and P0.1(CLKOUT) can not be output enabled
when the crystal oscillator is enabled. Output enables for these
pins are overridden by XOSC Enable.
SPI Use
The P1.3(SSEL), P1.4(SCLK), P1.5(SMOSI) and
P1.6(SMISO) pins can be used for their dedicated functions or
for GPIO. To enable the pin for GPIO, clear the corresponding
SPI Use bit. The SPI function controls the output enable for its
dedicated function pins when their GPIO enable bit is clear.
Figure 10. GPIO Block Diagram
V
CC
VREG
V
CC
VREG
GPIO
PIN
R
UP
Data Out
V
CC
GND
VREG
GND
3.3V Drive
Pull-Up Enable
Output Enable
Open Drain
Port Data
High Sink
Data In
TTL Threshold
(28 strony)
(88 strony)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji