CY7C601xx
CY7C602xx
Document 38-16016 Rev. *C Page 2 of 62
The enCoRe II LV features an internal oscillator. Optionally, an
external 1 MHz to 24 MHz crystal can be used to provide a
higher precision reference. The enCoRe II LV also supports
external clock
The enCoRe II LV has 8 Kbytes of Flash for user’s code and
256 bytes of RAM for stack space and user variables.
In addition, enCoRe II LV includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free-Running Timer with
Capture registers and a 12-bit Programmable Interval Timer.
The Power-on reset circuit detects when power is applied to
the device, resets the logic to a known state, and begins
executing instructions at Flash address 0x0000. When power
falls below a programmable trip voltage it generates a reset or
may be configured to generate an interrupt. There is a Low-
voltage detect circuit that detects when V
CC
drops below a
programmable trip voltage and it may be configurable to
generate a LVD interrupt to inform the processor about the
low-voltage event. POR and LVD share the same interrupt;
there is no separate interrupt for each. The Watchdog timer
can be used to ensure the firmware never gets stalled in an
infinite loop.
The microcontroller supports 17 maskable interrupts in the
vectored interrupt controller. All interrupts can be masked.
Interrupt sources include LVR/POR, a programmable interval
timer, a nominal 1.024-ms programmable output from the Free
Running Timer, two capture timers, five GPIO Ports, three
GPIO pins, two SPI, a 16-bit free-running timer wrap and an
internal wakeup timer interrupt. The wakeup timer causes
periodic interrupts when enabled. The capture timers interrupt
whenever a new timer value is saved due to a selected GPIO
edge event. A total of eight GPIO interrupts support both TTL
or CMOS thresholds. For additional flexibility, on the edge-
sensitive GPIO pins, the interrupt polarity is programmable to
be either rising or falling.
The free-running timer generates an interrupt at 1024-µs rate.
It can also generate an interrupt when the free-running counter
overflow occurs—every 16.384 ms. The timer can be used to
measure the duration of an event under firmware control by
reading the timer at the start and at the end of an event, then
calculating the difference between the two values. The two 8-
bit capture timer registers save a programmable 8-bit range of
the free-running timer when a GPIO edge occurs on the two
capture pins (P0.5, P0.6). The two 8-bit capture registers can
be ganged into a single 16-bit capture register.
The enCoRe II LV supports in-system programming by using
the P1.0 and P1.1 pins as the serial programming mode
interface.
Conventions
In this document, bit positions in the registers are shaded to
indicate which members of the enCoRe II LV family implement
the bits.
Logic Block Diagram
Figure 1. CY7C601xx/CY7C602xx Block Diagram
Available in all enCoRe II LV family members
CY7C601xx only
Internal
12 MHz
Oscillator
Clock
Control
Crystal
Oscillator
CY7C601xx only
POR /
Low-Voltage
Detect
Watchdog
Timer
M8C CPU
16 Extended
I/O Pins
16 GPIO
Pins
Wakeup
Timer
Capture
Timers
12-bit Timer
Vdd
Interrupt
Control
4 SPI/GPIO
Pins
Flash
8K Byte
RAM
256 Byte
(28 strony)
(88 strony)
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