Cypress Semiconductor CY14B256K Dokumentacja Pobierz pdf (Strona 19)

CY14B256K

Document Number: 001-06431 Rev. *G Page 19 of 24

Figure 7. SRAM Write Cycle 1: WE

Controlled

[26, 27]

Figure 8. SRAM Write Cycle 2: CE Controlled

Switching Waveforms (continued)

t

WC

t

SCE

t

HA

t

AW

t

SA

t

PWE

t

SD

t

HD

t

HZWE

t

LZWE

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

t

WC

ADDRESS

t

SA

t

SCE

t

HA

t

AW

t

PWE

t

SD

t

HD

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Note

27. CE

or WE are greater than V

IH

during address transitions.

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