Cypress Semiconductor Perform nvSRAM Instrukcja Użytkownika Pobierz pdf (Strona 9)

STK14D88

Document Number: 001-52037 Rev. *A Page 9 of 18

Software-Controlled STORE/RECALL Cycle

[13, 14]

No.

Symbols

Parameter

STK14D88-25 STK14D88-35 STK14D88-45

Unit Notes

E Cont

Alternate

Min Max Min Max Min Max

26 t

AVAV

STORE/RECALL Initiation Cycle Time 25 35 45 ns 14

AVEL

Address Setup Time 0 0 0 ns

ELEH

Clock Pulse Width 20 25 30 ns

EHAX

Address Hold Time 1 1 1 ns

RECALL

RECALL Duration 50 50 50 μs

Figure 9. E

and G Controlled Software STORE/RECALL Cycle

[14]

DATA VALID

HIGH IMPEDANCE

ADDRESS #6ADDRESS #1

DATA VALID

AVAV

DATA VALID

DQ (DATA

ADDRESS

23 30

STORE

/ t

RECALL

AVAV

AVEL

ELEH

ELAX

Notes

13.The software sequence is clocked on the falling edge of E

controlled READs.

14. The six consecutive addresses must be read in the order listed in the software STORE/RECALL Mode Selection Table. W

must be high during all six consecutive cycles

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