Cypress Semiconductor Perform nvSRAM Dokumentacja Pobierz pdf (Strona 22)

CY14B256KA

Document Number: 001-55720 Rev. *H Page 22 of 28

Software Controlled STORE/RECALL Cycle

Over the Operating Range

Parameter

[35, 36]

Description

25 ns 45 ns

Unit

Min Max Min Max

STORE/RECALL initiation cycle time 25 – 45 – ns

Address setup time 0 – 0 – ns

Clock pulse width 20 – 30 – ns

Address hold time 0 – 0 – ns

RECALL

RECALL duration – 200 – 200 µs

[37, 38]

Soft sequence processing time – 100 – 100 µs

Switching Waveforms

Figure 13. CE & OE Controlled Software STORE/RECALL Cycle

[36]

Figure 14. AutoStore Enable/Disable Cycle

[36]

LZCE

HZCE

STORE

RECALL

HHHD

LZHSB

High Impedance

Address #1 Address #6Address

HSB (STORE only)

DQ (DATA)

RWI

DELAY

Note

LZCE

HZCE

DELAY

Address #1 Address #6Address

DQ (DATA)

Note

RWI

Notes

35. The software sequence is clocked with CE

controlled or OE controlled reads.

36. The six consecutive addresses must be read in the order listed in Table 1. WE

must be HIGH during all six consecutive cycles.

37. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

38. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

39. DQ output data at the sixth read may be invalid since the output is disabled at t

DELAY

time.

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 28

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