CY7C1354V25
CY7C1356V25
PRELIMINARY
21
Switching Characteristics
Over the Operating Range
[16]
-200 -166 -133 -100
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
Clock
t
CYC
Clock Cycle Time 5 6 7.5 10.0 ns
F
MAX
Maximum Operating Frequency 200 166 133 100 MHz
t
CH
Clock HIGH 1.4 1.7 2.0 4.0 ns
t
CL
Clock LOW 1.4 1.7 2.0 4.0 ns
Output Times
t
CO
Data Output Valid After CLK Rise 3.2 3.5 4.2 5.0 ns
t
EOV
OE LOW to Output Valid
[15, 17, 19]
3.2 3.5 4.2 5.0 ns
t
DOH
Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 ns
t
CHZ
Clock to High-Z
[15, 16, 17, 18, 19]
1.5 3.2 1.5 3.5 1.5 3.5 1.5 3.5 ns
t
CLZ
Clock to Low-Z
[15, 16, 17, 18, 19]
1.5 1.5 1.5 1.5 ns
t
EOHZ
OE HIGH to Output High-Z
[16, 17, 19]
3.0 3.3 4.0 4.8 ns
t
EOLZ
OE LOW to Output Low-Z
[16, 17, 19]
0 0 0 0 ns
Set-Up Times
t
AS
Address Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
DS
Data Input Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
CENS
CEN Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
WES
WE, BWS
x
Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
ALS
ADV/LD Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 ns
t
CES
Chip Select Set-Up 1.5 1.5 2.0 2.0 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
CENH
CEN Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
WEH
WE, BW
x
Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.5 0.5 0.5 0.5 ns
t
CEH
Chip Select Hold After CLK Rise 0.5 0.5 0.5 0.5 ns
Shaded areas contain advance information.
Notes:
16. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified I
OL
/I
OH
and load capacitance. Shown in (a), (b) and (c) of AC test loads.
17. t
CHZ
, t
CLZ
, t
OEV
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
18. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
(50 strony)
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