Cypress Semiconductor CY7C1380FV25 Instrukcja Użytkownika Pobierz pdf

18-Mbit (512K x 36/1M x 18) Pipelined SRAM

CY7C1380DV25, CY7C1380FV25

CY7C1382DV25, CY7C1382FV25

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05546 Rev. *E Revised Feburary 15, 2007

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200, and 167 MHz

• Registered inputs and outputs for pipelined operation

• 2.5V core power supply

• Fast clock-to-output times, 2.6 ns (for 250-MHz device)

• Provides high-performance 3-1-1-1 access rate

• User selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1380DV25/CY7C1382DV25 available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 165-ball FBGA package.

CY7C1380FV25/CY7C1382FV25 available in Pb-free and

non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

Functional Description

[1]

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 SRAM integrates 512K x 36 and 1M x 18

SRAM cells with advanced synchronous peripheral circuitry

and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive edge triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE

), depth expansion chip enables (CE

and

[2]

), burst control inputs (ADSC, ADSP, and ADV), write

enables (BW

, and BWE), and global write (GW).

Asynchronous inputs include the output enable (OE

) and the

ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either address strobe processor (ADSP

) or

address strobe controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle.This part supports byte write

operations (see Pin Definitions on page 6 and Truth Table

[4,

5, 6, 7, 8]

on page 9 for further details). Write cycles can be one

to two or four bytes wide as controlled by the byte write control

inputs. GW

when active

LOW

causes all bytes to be written.

The CY7C1380DV25/CY7C1382DV25/CY7C1380FV25/

CY7C1382FV25 operates from a +2.5V core power supply

while all outputs may operate with a +2.5 supply. All inputs and

outputs are JEDEC-standard and JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

, CE

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable

[+] Feedback

1 2 3 4 5 6 ... 28 29

Podsumowanie treści

Strona 1 - CY7C1382DV25, CY7C1382FV25

18-Mbit (512K x 36/1M x 18) Pipelined SRAMCY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Cypress Semiconductor Corporation • 198 Champion Court •

Strona 2 - (1M x 18)

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 10 of 29Truth Table for Read/Write [6, 9]Function (CY7C1380DV25/

Strona 3 - Pin Configurations

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1380DV25/

Strona 4 - CY7C1380FV25 (512K x 36)

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 12 of 29Bypass RegisterTo save time when serially shifting data

Strona 5 - CY7C1382DV25 (1M x 18)

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 13 of 29instruction. When HIGH, it will enable the output buffer

Strona 6

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 14 of 292.5V TAP AC Test ConditionsInput pulse levels ...

Strona 7

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 15 of 29Identification CodesInstruction Code DescriptionEXTEST 0

Strona 8

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 16 of 29165-Ball BGA Boundary Scan Order[13, 15]Bit # Ball ID Bi

Strona 9

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 17 of 29Maximum RatingsExceeding the maximum ratings may impair

Strona 10

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 18 of 29Capacitance [18]Parameter Description Test Conditions100

Strona 11

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 19 of 29Switching CharacteristicsOver the Operating Range [19, 2

Strona 12

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 2 of 29Logic Block Diagram – CY7C1380DV25/CY7C1380FV25 [3] (512K

Strona 13

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 20 of 29Switching WaveformsRead Cycle Timing [25]tCYCtCLCLKADSPt

Strona 14

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 21 of 29Write Cycle Timing [25, 26]Switching Waveforms (continue

Strona 15

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 22 of 29Read/Write Cycle Timing [25, 27, 28]Switching Waveforms

Strona 16

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 23 of 29ZZ Mode Timing [29, 30]Switching Waveforms (continued)tZ

Strona 17

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 24 of 29Ordering InformationNot all of the speed, package, and t

Strona 18

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 25 of 29250 CY7C1380DV25-250AXC 51-85050 100-pin Thin Quad Flat

Strona 19

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 26 of 29Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Fla

Strona 20

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 27 of 29Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)Pack

Strona 21

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 28 of 29© Cypress Semiconductor Corporation, 2006-2007. The info

Strona 22

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 29 of 29Document History PageDocument Title: CY7C1380DV25/CY7C13

Strona 23

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 3 of 29Pin Configurations AAAAA1A0NC/72MNC/36MVSSVDDAAAAAAAADQPB

Strona 24

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVD

Strona 25

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 5 of 29Pin Configurations (continued)165-Ball FBGA Pinout (3 Ch

Strona 26

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 6 of 29Pin DefinitionsName IO DescriptionA0, A1, A Input-Synchro

Strona 27

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 7 of 29Functional OverviewAll synchronous inputs pass through in

Strona 28

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 8 of 29ADSP triggered write accesses require two clock cycles to

Strona 29

CY7C1380DV25, CY7C1380FV25CY7C1382DV25, CY7C1382FV25Document #: 38-05546 Rev. *E Page 9 of 29Truth Table [4, 5, 6, 7, 8] Operation Add. Used CE1CE2CE3

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