Cypress Semiconductor FX2LP Dokumentacja Pobierz pdf (Strona 5)

Migrating From EZ-USB FX2™ to EZ-USB FX2LP™

www.cypress.com Document No. 001-42079 Rev. *D 5

If the existing FX2 application is bus powered and uses

the double enumeration sequence (that is a recommended

workaround) to meet the unconfigured current

requirements of the USB-IF compliance test, then the

application does not behave the same when replaced with

the FX2LP. If replacing the part with FX2LP, when the

device enumerates with the high-speed chirp disabled

(control bit of the configuration byte of the EEPROM set),

on renumeration, the device fails to enumerate as a high-

speed device even though the 8051 had cleared bit 1 of

the CT1 register. The full-speed mode trick upon initial

plugin FX2 was done to get the unconfigured power-down

to the 100-mA range to meet the USB specification. As

FX2LP power is 50–60 mA maximum, not meeting the

unconfigured current limit when using the device as bus

powered is no longer an issue, there is no need to set this

control bit in the EEPROM anymore. The workaround is

not required anymore. Just have the FX2LP application

enumerate in USB high speed mode from the start.

For an FX2 bus-powered application that uses double

enumeration sequence to behave the same when

replaced with FX2LP, all you need to do is set the control

bit of the EEPROM to 0 (chirp enabled) and can leave the

firmware as is with the double enumeration workaround

code in it.

Automatic Disconnect and Reconnect on

Hard Reset

The FX2LP has an enhanced capability of disconnecting

and reconnecting on a hard reset, when the RESET# is

asserted by the external peripheral.

The FX2 does not cause a disconnect on a hard reset

(RESET# asserted). On releasing the reset the FX2 no

longer responds to the host since it does not have a valid

address anymore. To resume communication with the host

the 8051 must cause a disconnect and a reconnect by

setting DISCON bit of the USBCS register and

subsequently clearing. On a reconnect event the host

issues a SET_ADDRESS request and re-enumerate the

device.

In the case of an FX2LP, the device does a disconnect

and a reconnect automatically on a hard reset. When the

RESET# is asserted, the FX2LP resets the FNADDR

(function address) register to 0x00. On releasing the

reset# the FX2LP automatically does a disconnect

followed by a reconnect. If using FX2LP the 8051 does not

need to be programmed to do the disconnect and

reconnect by setting and clearing the DISCON bit

manually.

Expanded Code/Data RAM

The FX2LP has 16 Kbytes of internal Code/Data RAM,

where the FX2 had only 8 Kbytes. The additional RAM is

located in the address space of 0x2000 to 0x3FFF. If the

firmware of the existing design is completely internal to the

FX2, no changes are required to use the FX2LP. If the

FX2 design had RAM at this location, no changes are

required. The FX2LP accesses the internal RAM instead

of the external RAM.

If there was either memory mapped ROM (any nonvolatile

memory) or memory mapped I/O within these locations,

they must be mapped to new locations and the firmware

should be re linked. In the limited number of designs that

require this change, just a logic change to a FPGA or

programmable logic array for hardware memory decoding

and changing the target location of the external code

within the compiler/linker is required.

In most designs it is felt that the external memory map

would not have used this location in memory. Less logic is

required to locate the memory at higher locations and

therefore it is believed that most designs would have used

a higher address, such as 0x8000, to start the external

memory. If this is the case, no modifications, other then

the required crystal modifications, are required.

Zero-length INPackets with No Firmware

Intervention and Data PID Sequencing for

ISO Transfers

The FX2LP has the capability of sending a zero-length

isochronous data packet (ZLP) when the host issues an IN

token to an isochronous IN endpoint FIFO and the SIE

does not have any data packets available.

This feature is very useful when designing high-bandwidth

isochronous applications. When an isochronous IN

endpoint is configured for greater than one packet per

microframe, there is a possibility of the core not having

more than one packet available in a microframe. In this

case, when the host issues an IN token, the FX2LP core

sends a zero-length packet with the appropriate data PID

automatically. Hence avoiding the occurrence of a

scenario where the host may encounter a turnaround time-

out error on not receiving any data when requesting more

than one packet per microframe.

In the Technical Reference Manual, register

EPxISOINPKTS (x = Endpoint number) defines an

additional bit called: ADDJ. This bit defaults to a zero

value. In this condition, FX2LP operates the same as the

FX2.

The auto adjust (AADJ) feature was useful when

designing with the FX2LP engineering samples provided

at the early stages of the FX2LP development. These

engineering samples did not have the ability to issue a

zero-length isochronous packets automatically and hence

were prone to running into a DATA PID mismatch scenario

when dealing with high-bandwidth ISO IN transfer (please

see the “Streaming Data Through Isochronous/Bulk

Endpoints on EZ-USB FX2™ EZ-USB FX2LP™ -

AN4053” application note for further information on DATA

PID mismatch issue). The auto adjust feature is a

workaround to the data PID mismatch issue and to use

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