Cypress Semiconductor FX2LP Instrukcja Użytkownika Pobierz pdf (Strona 49)

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

Document #: 38-08032 Rev. *K Page 49 of 60

10.15 Slave FIFO Synchronous Address

10.16 Slave FIFO Asynchronous Address

Table 10-17. Slave FIFO Synchronous Address Parameters

[21]

Parameter Description Min. Max. Unit

IFCLK

Interface Clock Period 20.83 200 ns

SFA

FIFOADR[1:0] to Clock Set-up Time 25 ns

FAH

Clock to FIFOADR[1:0] Hold Time 10 ns

Slave FIFO Asynchronous Address Parameters

[23]

Parameter Description Min. Max. Unit

SFA

FIFOADR[1:0] to SLRD/SLWR/PKTEND Set-up Time 10 ns

FAH

RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns

IFCLK

SLCS/FIFOADR [1:0]

SFA

FAH

Figure 10-16. Slave FIFO Synchronous Address Timing Diagram

[20]

SLRD/SLWR/PKTEND

SLCS/FIFOADR [1:0]

SFA

FAH

Figure 10-17. Slave FIFO Asynchronous Address Timing Diagram

[20]

1 2 ... 44 45 46 47 48 49 50 51 52 53 54 ... 59 60

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Cypress Semiconductor FX2LP Instrukcja Użytkownika Strona 49