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CY7C1526KV18

CY7C1513KV18

CY7C1515KV18

72-Mbit QDR

II SRAM Four-Word

Burst Architecture

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-00435 Rev. *R Revised January 7, 2014

72-Mbit QDR

II SRAM Four-Word Burst Architecture

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 333 MHz clock for high bandwidth

■ Four-word burst for reducing address bus frequency

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 666 MHz) at 333 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR

II operates with 1.5 cycle read latency when DOFF is

asserted HIGH

■ Operates similar to QDR I device with one cycle read latency

when DOFF

is asserted Low

■ Available in x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8 V (±0.1 V); I/O V

DDQ

= 1.4 V to V

❐ Supports both 1.5 V and 1.8 V I/O supply

■ Available in 165-ball fine pitch ball grid array (FBGA) package

(13 × 15 × 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Phase-locked loop (PLL) for accurate data placement

Configurations

CY7C1526KV18 – 8 M × 9

CY7C1513KV18 – 4 M × 18

CY7C1515KV18 – 2 M × 36

Functional Description

The CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18

are 1.8-V synchronous pipelined SRAMs, equipped with QDR II

architecture. QDR II architecture consists of two separate ports:

the read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to “turnaround” the

data bus that exists with common I/O devices. Each port can be

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR II read and write ports are

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 9-bit words

(CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit

words (CY7C1515KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

), memory bandwidth is maximized while simplifying

system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz Unit

Maximum operating frequency 333 300 250 200 MHz

Maximum operating current × 9 600 560 490 Not Offered mA

× 18 620 570 500 440

× 36 850 790 680 Not Offered

1 2 3 4 5 6 ... 34 35

Podsumowanie treści

Strona 1 - Burst Architecture

CY7C1526KV18CY7C1513KV18CY7C1515KV1872-Mbit QDR® II SRAM Four-WordBurst ArchitectureCypress Semiconductor Corporation • 198 Champion Court • San Jose,

Strona 2

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 10 of 35initiated on two consecutive K clock rises. The internal logic of

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 11 of 35Application ExampleFigure 2 shows four QDR II used in an applicat

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 12 of 35Truth TableThe truth table for CY7C1526KV18, CY7C1513KV18, and CY

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 13 of 35Write Cycle DescriptionsThe write cycle description table for CY7

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 14 of 35IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorporate a

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 15 of 35IDCODEThe IDCODE instruction loads a vendor-specific, 32-bit code

Strona 8

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 16 of 35TAP Controller State DiagramThe state diagram for the TAP control

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 17 of 35TAP Controller Block Diagram0012..293031Boundary Scan RegisterIde

Strona 10 - CY7C1515KV18

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 18 of 35TAP AC Switching CharacteristicsOver the Operating RangeParameter

Strona 11

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 19 of 35TAP Timing and Test ConditionsFigure 3 shows the TAP timing and t

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 2 of 35Logic Block Diagram – CY7C1526KV18CLKA(20:0)Gen.KKControlLogicAddr

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 20 of 35Identification Register DefinitionsInstruction FieldValueDescript

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 21 of 35Boundary Scan OrderBit # Bump ID Bit # Bump ID Bit # Bump ID Bit

Strona 15

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 22 of 35Power-Up Sequence in QDR II SRAMQDR II SRAMs must be powered up a

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 23 of 35Maximum RatingsExceeding maximum ratings may impair the useful li

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 24 of 35IDD [27]VDD operating supply VDD = Max, IOUT = 0 mA,f = fMAX = 1/

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 25 of 35AC Electrical CharacteristicsOver the Operating RangeParameter [2

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 26 of 35Switching CharacteristicsOver the Operating Range [31, 32]Cypress

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 27 of 35Output TimestCOtCHQVC/C clock rise (or K/K in single clock mode)

Strona 21

CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 28 of 35Switching WaveformsFigure 6. Read/Write/Deselect Sequence [37, 3

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 29 of 35Ordering InformationCypress offers other versions of this type of

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 3 of 35Logic Block Diagram – CY7C1513KV18CLKA(19:0)Gen.KKControlLogicAddr

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 30 of 35Ordering Code DefinitionsTemperature Range: X = C or IC = Commerc

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 31 of 35Package DiagramFigure 7. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 32 of 35Acronyms Document ConventionsUnits of MeasureAcronym DescriptionB

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 33 of 35Document History PageDocument Title: CY7C1526KV18/CY7C1513KV18/CY

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 34 of 35*H 2797196 VKN / AESA11/03/09 Updated Ordering Information:Includ

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Document Number: 001-00435 Rev. *R Revised January 7, 2014 Page 35 of 35QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 4 of 35Logic Block Diagram – CY7C1515KV18512K x 36 ArrayCLKA(18:0)Gen.KKC

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 5 of 35ContentsPin Configurations ...

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 6 of 35Pin ConfigurationsThe pin configurations for CY7C1526KV18, CY7C151

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 7 of 35CY7C1515KV18 (2 M × 36)1 2 3 4 5 6 7 8 9 10 11A CQ NC/288M A WPS B

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 8 of 35Pin DefinitionsPin Name I/O Pin DescriptionD[x:0]Input-Synchronous

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CY7C1526KV18CY7C1513KV18CY7C1515KV18Document Number: 001-00435 Rev. *R Page 9 of 35Functional OverviewThe CY7C1526KV18, CY7C1513KV18, CY7C1515KV18 ar

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