Cypress Semiconductor MoBL-USB CY7C68053 Dokumentacja

CY7C68053MoBL-USB™ FX2LP18 USBMicrocontrollerCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document #

CY7C68053Document # 001-06120 Rev *J Page 10 of 423.14.1 Three Control OUT SignalsThe 56-pin package brings out three of these signals, CTL0–CTL2. T

CY7C68053Document # 001-06120 Rev *J Page 11 of 423.18.2 I2C Interface Boot Load AccessAt power on reset the I2C interface boot loader loads the VID

CY7C68053Document # 001-06120 Rev *J Page 12 of 42Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View12345678ABCDEFGH1A 2A 3A 4A 5A 6A 7A 8A1

CY7C68053Document # 001-06120 Rev *J Page 13 of 424.1 CY7C68053 Pin Descriptions Note9. Do not leave unused inputs floating. Tie either HIGH or LOW

CY7C68053Document # 001-06120 Rev *J Page 14 of 426F PA4 orFIFOADR0I/O/Z I(PA4)Multiplexed pin whose function is selected by IFCONFIG[1:0].PA4 is a b

CY7C68053Document # 001-06120 Rev *J Page 15 of 42PORT D8A PD0 orFD[8]I/O/Z I(PD0)Multiplexed pin whose function is selected by the IFCONFIG[1:0] and

CY7C68053Document # 001-06120 Rev *J Page 16 of 427B WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the oscil-l

CY7C68053Document # 001-06120 Rev *J Page 17 of 425. Register SummaryFX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in g

CY7C68053Document # 001-06120 Rev *J Page 18 of 42E62C 1 ECC1B2 ECC1 Byte 2 address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 00000000 RE62D 1 ECC2

CY7C68053Document # 001-06120 Rev *J Page 19 of 42E65E 1 EPIE Endpoint interrupt enablesEP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RWE65F 1 E

CY7C68053Document # 001-06120 Rev *J Page 2 of 42ContentsApplications ...3Function

CY7C68053Document # 001-06120 Rev *J Page 20 of 42E6A2 1 EP1INCS Endpoint 1 IN control and status0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrbE6A3 1 EP2CS

CY7C68053Document # 001-06120 Rev *J Page 21 of 42ReservedE6D2 1 EP2GPIFFLGSEL[10]Endpoint 2 GPIF flag select0 0 0 0 0 0 FS1 FS0 00000000 RWE6D3 1 EP

CY7C68053Document # 001-06120 Rev *J Page 22 of 42Special Function Registers (SFRs)80 1 IOA[13]Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxx

CY7C68053Document # 001-06120 Rev *J Page 23 of 42C0 1 SCON1[13]Serial Port 1 Control (bit addressable)SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1

CY7C68053Document # 001-06120 Rev *J Page 24 of 426. Absolute Maximum RatingsExceeding maximum ratings may shorten the useful life of the device. Us

CY7C68053Document # 001-06120 Rev *J Page 25 of 429. AC Electrical Characteristics9.1 USB TransceiverUSB 2.0-compliant in full and high speed modes

CY7C68053Document # 001-06120 Rev *J Page 26 of 4289.3 Slave FIFO Synchronous ReadNotes16. Dashed lines denote signals with programmable polarity.17

CY7C68053Document # 001-06120 Rev *J Page 27 of 429.4 Slave FIFO Asynchronous ReadTable 13. Slave FIFO Synchronous Read Parameters with Externally

CY7C68053Document # 001-06120 Rev *J Page 28 of 429.5 Slave FIFO Synchronous WriteZZtSFDtFDHDATAIFCLKSLWRFLAGStWRHtXFLGtIFCLKtSWRNFigure 11. Slave

CY7C68053Document # 001-06120 Rev *J Page 29 of 429.6 Slave FIFO Asynchronous Write9.7 Slave FIFO Synchronous Packet End StrobeDATAtSFDtFDHFLAGStXF

CY7C68053Document # 001-06120 Rev *J Page 3 of 42Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18 (CY7C68053) is a low voltage (1.8 V) version o

CY7C68053Document # 001-06120 Rev *J Page 30 of 42There is no specific timing requirement to be met for asserting the PKTEND pin with regards to asse

CY7C68053Document # 001-06120 Rev *J Page 31 of 429.9 Slave FIFO Output Enable 9.10 Slave FIFO Address to Flags/Data Table 21. Slave FIFO Output E

CY7C68053Document # 001-06120 Rev *J Page 32 of 429.11 Slave FIFO Synchronous Address 9.12 Slave FIFO Asynchronous Address Table 23. Slave FIFO S

CY7C68053Document # 001-06120 Rev *J Page 33 of 429.13 Sequence DiagramVarious sequence diagrams and examples are presented in this section.9.13.1

CY7C68053Document # 001-06120 Rev *J Page 34 of 429.13.2 Single and Burst Synchronous Write Figure 22 shows the timing relationship of the SLAVE FIF

CY7C68053Document # 001-06120 Rev *J Page 35 of 429.13.3 Sequence Diagram of a Single and Burst Asynchronous Read Figure 23 illustrates the timing r

CY7C68053Document # 001-06120 Rev *J Page 36 of 429.13.4 Sequence Diagram of a Single and Burst Asynchronous Write Figure 25 illustrates the timing

CY7C68053Document # 001-06120 Rev *J Page 37 of 4210. Ordering InformationTable 24 lists the key package features and ordering codes. The table cont

CY7C68053Document # 001-06120 Rev *J Page 38 of 4211. Package DiagramThe FX2LP18 is available in a 56-pin VFBGA package.Figure 26. 56 VFBGA (5 × 5

CY7C68053Document # 001-06120 Rev *J Page 39 of 4212. PCB Layout RecommendationsThe following recommendations must be followed to ensure reliable hi

CY7C68053Document # 001-06120 Rev *J Page 4 of 423.3 I2C™ BusFX2LP18 supports the I2C bus as a master only at 100 or 400 KHz. SCL and SDA pins have

CY7C68053Document # 001-06120 Rev *J Page 40 of 4213. Acronyms 14. Document ConventionsUnits of MeasureTable 25. Acronyms Used in this DocumentAcr

CY7C68053Document # 001-06120 Rev *J Page 41 of 42Document History Page Document Title: CY7C68053 MoBL-USB™ FX2LP18 USB MicrocontrollerDocument Numbe

Document # 001-06120 Rev *J Revised October 28, 2010 Page 42 of 42Purchase of I2C components from Cypress, or one of its sublicensed Associated Compa

CY7C68053Document # 001-06120 Rev *J Page 5 of 42If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP18 substitutes its INT2V

CY7C68053Document # 001-06120 Rev *J Page 6 of 423.9 Reset and WakeupThe reset and wakeup pins are described in detail in this section.3.9.1 Reset

CY7C68053Document # 001-06120 Rev *J Page 7 of 42 CTL0-2. If tri-stated via GPIFIDLECTL, these pins must be pulled to VCC_IO or GND or driven by ano

CY7C68053Document # 001-06120 Rev *J Page 8 of 423.12.4 Endpoint Configurations (High Speed Mode)Endpoints 0 and 1 are the same for every configurat

CY7C68053Document # 001-06120 Rev *J Page 9 of 423.12.6 Default High Speed Alternate Settings3.13 External FIFO InterfaceThe architecture, control