Cypress Semiconductor CY7C1515JV18 Instrukcja Użytkownika Pobierz pdf

72-Mbit QDR™-II SRAM 4-Word

Burst Architecture

CY7C1511JV18, CY7C1526JV18

CY7C1513JV18, CY7C1515JV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-12560 Rev. *C Revised March 10, 2008

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ 300 MHz clock for high bandwidth

■ 4-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces on both read and write ports

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ QDR-II operates with 1.5 cycle read latency when the Delay

Lock Loop (DLL) is enabled

■ Operates like a QDR-I device with 1 cycle read latency in DLL

off mode

■ Available in x8, x9, x18, and x36 configurations

■ Full data coherency, providing most current data

■ Core V

= 1.8 (± 0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ Variable drive HSTL output buffers

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1511JV18 – 8M x 8

CY7C1526JV18 – 8M x 9

CY7C1513JV18 – 4M x 18

CY7C1515JV18 – 2M x 36

Functional Description

The CY7C1511JV18, CY7C1526JV18, CY7C1513JV18, and

CY7C1515JV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turn-around” the data bus that exists with common

IO devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR-II read and write ports are completely independent

of one another. To maximize data throughput, both read and write

ports are equipped with DDR interfaces. Each address location

is associated with four 8-bit words (CY7C1511JV18), 9-bit words

(CY7C1526JV18), 18-bit words (CY7C1513JV18), or 36-bit

words (CY7C1515JV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz Unit

Maximum Operating Frequency 300 MHz

Maximum Operating Current x8 1090 mA

x9 1090

x18 1115

x36 1140

[+] Feedback

1 2 3 4 5 6 ... 26 27

Podsumowanie treści

Strona 1 - Burst Architecture

72-Mbit QDR™-II SRAM 4-WordBurst ArchitectureCY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Cypress Semiconductor Corporation • 198 Champion Cour

Strona 2

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 10 of 27Application ExampleFigure 1 shows four QDR-II used

Strona 3

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 11 of 27Write Cycle Descriptions The write cycle descripti

Strona 4

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 12 of 27Write Cycle DescriptionsThe write cycle descriptio

Strona 5

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 13 of 27IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs

Strona 6

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 14 of 27IDCODEThe IDCODE instruction loads a vendor-specif

Strona 7

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 15 of 27TAP Controller State DiagramThe state diagram for

Strona 8

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 16 of 27TAP Controller Block DiagramTAP Electrical Charact

Strona 9

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 17 of 27TAP AC Switching Characteristics Over the Operatin

Strona 10 - CY7C1513JV18, CY7C1515JV18

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 18 of 27Identification Register Definitions Instruction Fi

Strona 11

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 19 of 27Boundary Scan Order Bit # Bump ID Bit # Bump ID Bi

Strona 12

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 2 of 27Logic Block Diagram (CY7C1511JV18)Logic Block Diagr

Strona 13

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 20 of 27Power Up Sequence in QDR-II SRAMQDR-II SRAMs must

Strona 14

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 21 of 27Maximum RatingsExceeding maximum ratings may impai

Strona 15

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 22 of 27CapacitanceTested initially and after any design o

Strona 16

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 23 of 27Switching CharacteristicsOver the Operating Range

Strona 17 - [+] Feedback

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 24 of 27Switching WaveformsFigure 3. Read/Write/Deselect

Strona 18

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 25 of 27Ordering Information Not all of the speed, package

Strona 19

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 26 of 27Package DiagramFigure 4. 165-ball FBGA (15 x 17 x

Strona 20 - Power Up Waveforms

Document Number: 001-12560 Rev. *C Revised March 10, 2008 Page 27 of 27QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by

Strona 21 - Operating Range

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 3 of 27Logic Block Diagram (CY7C1513JV18)Logic Block Diagr

Strona 22 - Thermal Resistance

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 4 of 27Pin ConfigurationThe pin configuration for CY7C1511

Strona 23

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 5 of 27CY7C1513JV18 (4M x 18)1234567891011A CQNC/144M A WP

Strona 24 - Switching Waveforms

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 6 of 27Pin Definitions Pin Name IO Pin DescriptionD[x:0]In

Strona 25

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 7 of 27CQ Echo Clock CQ is Referenced with Respect to C. T

Strona 26 - Package Diagram

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 8 of 27Functional OverviewThe CY7C1511JV18, CY7C1526JV18,

Strona 27

CY7C1511JV18, CY7C1526JV18CY7C1513JV18, CY7C1515JV18Document Number: 001-12560 Rev. *C Page 9 of 27Concurrent TransactionsThe read and write ports on