Cypress Semiconductor CY7C1440AV33 Instrukcja Użytkownika Pobierz pdf

36-Mbit (1M x 36/2M x 18/512K x 72)

Pipelined Sync SRAM

CY7C1440AV33

CY7C1442AV33

CY7C1446AV33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05383 Rev. *E Revised June 23, 2006

Features

• Supports bus operation up to 250 MHz

• Available speed grades are 250, 200 and 167 MHz

• Registered inputs and outputs for pipelined operation

• 3.3V core power supply

• 2.5V/3.3V I/O power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous output enable

• Single Cycle Chip Deselect

• CY7C1440AV33, CY7C1442AV33 available in lead-free

100-pin TQFP package, lead-free and non-lead-free

165-ball FBGA package. CY7C1446AV33 available in

lead-free and non-lead-free 209-ball FBGA package

• Also available in lead-free packages

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• “ZZ” Sleep Mode Option

Functional Description

[1]

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33 SRAM

integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with

advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC

, ADSP, and ADV), Write Enables (BW

and BWE), and Global Write (GW). Asynchronous inputs

include the Output Enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP

) or

Address Strobe Controller (ADSC

) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two or four bytes wide as

controlled by the byte write control inputs. GW when active

LOW

causes all bytes to be written.

The CY7C1440AV33/CY7C1442AV33/CY7C1446AV33

operates from a +3.3V core power supply while all outputs may

operate with either a +2.5 or +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.2 3.4 ns

Maximum Operating Current 475 425 375 mA

Maximum CMOS Standby Current 120 120 120 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Podsumowanie treści

Strona 1 - Pipelined Sync SRAM

36-Mbit (1M x 36/2M x 18/512K x 72)Pipelined Sync SRAMCY7C1440AV33CY7C1442AV33CY7C1446AV33Cypress Semiconductor Corporation • 198 Champion Court • S

Strona 2

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 10 of 31READ Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-StateREAD C

Strona 3

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 11 of 31IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1440AV33/CY7C1442AV33/CY

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 12 of 31Performing a TAP ResetA RESET is performed by forcing TMS HIGH (VDD) fo

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 13 of 31The shifting of data for the SAMPLE and PRELOAD phasescan occur concurr

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 14 of 313.3V TAP AC Test ConditionsInput pulse levels ...

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 15 of 31 TAP DC Electrical Characteristics And Operating Conditions (0°C <

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 16 of 31 Notes: 14. Balls that are NC (No Connect) are preset LOW.15. Bit# 89 i

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 17 of 31 Note: 16. Bit# 138 is preset HIGH.209-ball FBGA Boundary Scan Order [1

Strona 10 - CY7C1446AV33

CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 18 of 31Maximum Ratings(Above which the useful life may be impaired. For user g

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 19 of 31Capacitance[19]Parameter Description Test Conditions100 TQFPMax.165 FBG

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 2 of 31Logic Block Diagram – CY7C1440AV33 (1M x 36)ADDRESSREGISTERADVCLKBURSTCO

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 20 of 31Switching Characteristics Over the Operating Range[24, 25]Parameter Des

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 21 of 31Switching WaveformsRead Cycle Timing[26]Note: 26. On this diagram, when

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 22 of 31Write Cycle Timing[26, 27]Note: 27.Full width write can be initiated by

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 23 of 31Read/Write Cycle Timing[26, 28, 29]Notes: 28. The data bus (Q) remains

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 24 of 31ZZ Mode Timing[30, 31]Notes: 30. Device must be deselected when enterin

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 25 of 31Ordering InformationNot all of the speed, package and temperature range

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 26 of 31250 CY7C1440AV33-250AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 27 of 31Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 28 of 31Package Diagrams (continued)A1PIN 1 CORNER17.00±0.1015.00±0.107.001.00

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 29 of 31© Cypress Semiconductor Corporation, 2006. The information contained he

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 3 of 31BWDBWCBWBBWABWEGWCE1CE2CE3OEENABLEREGISTERPIPELINEDENABLEADDRESSREGISTER

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 30 of 31Document History PageDocument Title: CY7C1440AV33/CY7C1442AV33/CY7C1446

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 31 of 31*E 473650 See ECN VKN Added the Maximum Rating for Supply Voltage on VD

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 4 of 31Pin Configurations DQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQBVSSNCVDDZ

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 5 of 31Pin Configurations (continued)165-ball FBGA (15 x 17 x 1.4 mm) Pinout C

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 6 of 31209-ball FBGA (14 x 22 x 1.76 mm) PinoutCY7C1446AV33 (512K × 72)Pin Conf

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 7 of 31CE2Input-SynchronousChip Enable 2 Input, active HIGH. Sampled on the ris

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 8 of 31Functional OverviewAll synchronous inputs pass through input registers c

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CY7C1440AV33CY7C1442AV33CY7C1446AV33Document #: 38-05383 Rev. *E Page 9 of 31 Interleaved Burst Address Table (MODE = Floating or VDD)FirstAddressA1

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