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36-Mbit QDR-II™ SRAM 2-Word Burst

Architecture

CY7C1410AV18

CY7C1425AV18

CY7C1412AV18

CY7C1414AV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05615 Rev. *C Revised June 26, 2006

Features

• Separate Independent Read and Write data ports

— Supports concurrent transactions

• 250-MHz clock for high bandwidth

• 2-Word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 500 MHz) @ 250 MHz

• Two input clocks (K and K

) for precise DDR timing

— SRAM uses rising edges only

• Two input clocks for output data (C and C

) to minimize

clock-skew and flight-time mismatches

• Echo clocks (CQ and CQ

) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x9, x18, and x36 configurations

• Full data coherency, providing most current data

•Core V

= 1.8V (±0.1V); I/O V

DDQ

= 1.4V to V

• Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

• Offered in both lead-free and non lead-free packages

• Variable drive HSTL output buffers

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1410AV18 – 4M x 8

CY7C1425AV18 – 4M x 9

CY7C1412AV18 – 2M x 18

CY7C1414AV18 – 1M x 36

Functional Description

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and

CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR™-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. The Read address is latched on the

rising edge of the K clock and the Write address is latched on

the rising edge of the K

clock. Accesses to the QDR-II Read

and Write ports are completely independent of one another. In

order to maximize data throughput, both Read and Write ports

are equipped with Double Data Rate (DDR) interfaces. Each

address location is associated with two 8-bit words

(CY7C1410AV18) or 9-bit words (CY7C1425AV18) or 18-bit

words (CY7C1412AV18) or 36-bit words (CY7C1414AV18)

that burst sequentially into or out of the device. Since data can

be transferred into and out of the device on every rising edge

of both input clocks (K and K

and C and C), memory bandwidth

is maximized while simplifying system design by eliminating

bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 250 200 167 MHz

Maximum Operating Current 1065 870 740 mA

[+] Feedback

1 2 3 4 5 6 ... 24 25

Podsumowanie treści

Strona 1 - Architecture

36-Mbit QDR-II™ SRAM 2-Word BurstArchitectureCY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Cypress Semiconductor Corporation • 198 Champion Court •

Strona 2

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 10 of 25L H – L-H During the Data portion of a Write sequence: CY7C

Strona 3

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 11 of 25IEEE 1149.1 Serial Boundary Scan (JTAG)These SRAMs incorpor

Strona 4

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 12 of 25is loaded into the instruction register upon power-up orwhe

Strona 5

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 13 of 25 Note: 9. The 0/1 next to each state represents the value a

Strona 6

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 14 of 25 TAP Controller Block Diagram0012..293031Boundary Scan Reg

Strona 7

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 15 of 25 TAP AC Switching Characteristics Over the Operating Range

Strona 8

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 16 of 25Identification Register DefinitionsInstruction FieldValueDe

Strona 9

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 17 of 25Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump

Strona 10 - CY7C1414AV18

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 18 of 25Power-Up Sequence in QDR-II SRAM[13, 14]QDR-II SRAMs must b

Strona 11

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 19 of 25Maximum Ratings(Above which the useful life may be impaired

Strona 12

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 2 of 25Logic Block Diagram (CY7C1410AV18)CLKA(20:0)Gen.KKControlLog

Strona 13

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 20 of 25Thermal Resistance[21]Parameter Description Test Conditions

Strona 14 - [+] Feedback

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 21 of 25 Switching Characteristics Over the Operating Range[22, 23]

Strona 15

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 22 of 25Switching Waveforms[28, 29, 30]Read/Write/Deselect Sequence

Strona 16

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 23 of 25Ordering InformationNot all of the speed, package and tempe

Strona 17

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 24 of 25© Cypress Semiconductor Corporation, 2006. The information

Strona 18

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 25 of 25Document History PageDocument Title: CY7C1410AV18/CY7C1425A

Strona 19

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 3 of 25 Logic Block Diagram (CY7C1412AV18)CLKA(19:0)Gen.KKControlLo

Strona 20

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 4 of 25Pin Configurations CY7C1410AV18 (4M x 8) 2345671ABCDEFGHJKLM

Strona 21

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 5 of 25Pin Configurations (continued)CY7C1412AV18 (2M x 18) 234 56

Strona 22

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 6 of 25Pin Definitions Pin Name I/O Pin DescriptionD[x:0]Input-Sync

Strona 23

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 7 of 25Functional OverviewThe CY7C1410AV18, CY7C1425AV18, CY7C1412A

Strona 24

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 8 of 25Read OperationsThe CY7C1412AV18 is organized internally as 2

Strona 25

CY7C1410AV18CY7C1425AV18CY7C1412AV18CY7C1414AV18Document #: 38-05615 Rev. *C Page 9 of 25 Application Example[1]Truth Table[2, 3, 4, 5, 6, 7] Oper

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